DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed on September 27, 2024 and May 27, 2025 have been considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 18-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kanbe et al (JP 2000-101245; cited in the IDS; hereinafter Kanbe).
Regarding claim 1, Kanbe discloses an electronic system (see figure 1), comprising: a base (100) having a device-attach region, wherein the base (100) comprises: a build-up layer structure (see figure 1) ; a vertical interconnect structure passing (see figure 1) through the build-up layer structure and located in the device-attach region, wherein the vertical interconnect structure (see figure 1) comprises at least one buried via (36) and at least one blind (57) via electrically coupled to the buried via (see figure 1); and a first through via (56) passing through the build-up layer structure and located in the device-attach region (see figure 1), wherein the first through via (56) is a straight through via (see figure 1); and a semiconductor device (paragraph 0025) mounted on the device-attach region of the base.
Regarding claim 2, Kanbe discloses the electronic system (see figure 1), wherein the base (100) further comprises: a first ground plane (51) disposed on a top surface of the build-up layer structure and located in the device-attach region; wherein the first through via (56) is coupled to the first ground plane.
Regarding claim 3, Kanbe discloses the electronic system (see figure 1), wherein the semiconductor device (paragraph 0025) is mounted on the device-attach region of the base (100) by a plurality of conductive structures (solders), wherein the base (100) further comprises a first conductive layer (53) disposed on the top surface of the build-up layer structure (see figure 1), wherein the first conductive layer (53) comprises the first ground plane (51) comprising at least one ground pad (71) in the device-attach region (see figure 1), wherein the plurality of conductive structures (solders) comprise at least one grounded conductive structure disposed in contact with the ground pad (71), and wherein the ground pad (71) is disposed in contact with the vertical interconnect structure (see figure 1) corresponding to the conductive structure of the semiconductor device (paragraph 0025).
Regarding claim 4, Kanbe discloses the electronic system (see figure 1), wherein the ground pad (71) is offset from the first through via (56) along a first direction, wherein the first direction is substantially parallel to the top surface of the base (see figure 1).
Regarding claim 18, Kanbe discloses an electronic system (see figure 1), comprising: a base (100) having a device-attach region, wherein the base (100) comprises: a build-up layer structure (see figure 1); and a through via (56) passing through the build-up layer structure (see figure 1) and located in the device-attach region, wherein the first through via (56) is a straight through via; and a semiconductor device mounted on the device-attach region (paragraph 0025).
Regarding claim 19, Kanbe discloses the electronic system (see figure 1), wherein the base (100) further comprises: a first ground plane (51) disposed on a top surface of the build-up layer structure, wherein the through via (56) is coupled to the first ground plane (see figure 1).
Regarding claim 20, Kanbe discloses the electronic system (see figure 1), wherein the base (100) further comprises: a vertical interconnect structure (see figure 1) passing through the build-up layer structure (see figure 1) and located in the device-attach region, wherein the vertical interconnect structure (see figure 1) comprises at least one buried via (36) and at least one blind via (57) electrically coupled to the buried via (36), wherein the semiconductor device (paragraph 0025) is mounted on the device-attach region of the base (100) by at least one grounded conductive structure (53) connecting to the through via (56), and wherein the at least one grounded conductive structure (53) is disposed directly above the vertical interconnect structure (see figure 1) rather than above the through via.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kanbe et al (JP 2000-101245; cited in the IDS; hereinafter Kanbe) in view of Nakazawa et al (US 9,474,166; hereinafter Nakazawa).
Regarding claim 5, Kanbe discloses the electronic system (see figure 1), wherein the base (100) further comprises: a first solder mask layer (63) disposed on the first conductive layer (53); but Kanbe lacks the first solder mask layer having a first opening to expose the first through via. Nakazawa teaches an electronic system, comprising: a base (100) having a device-attach region, wherein the base (100) comprises: a build-up layer structure (see figure 1b) ; and a first through via (121) passing through the build-up layer structure and located in the device-attach region (see figure 1b), wherein the first through via (121) is a straight through via (see figure 1b); and a semiconductor device (201) mounted on the device-attach region of the base; a first solder mask layer (150) disposed on the first conductive layer (101); the first solder mask layer (150) has a first opening to expose the first through via (column 4 lines 34-49; see figure 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide to Kanbe’s electronic system with the first solder mask having a first opening to exposed the first through hole as taught by Nakazawa to improve heat dissipation.
Regarding claim 6, the modified Kanbe discloses the electronic system (see figure 1), wherein the ground pad (71) and a portion of the first ground plane (51) adjacent to the ground pad (71) are exposed from the first opening (as taught by Nakazawa) and/or a portion of the first ground plane (51) adjacent to the first through via (56) is exposed from the first opening (as taught by Nakazawa).
Regarding claim 7, the modified Kanbe discloses the electronic system (see figure 1), wherein the at least one grounded conductive structure (solder) adjacent to the first through via (56) is exposed by the first opening (as taught by Nakazawa).
Regarding claim 8, the modified Kanbe discloses the electronic system (see figure 1), wherein the base (100) further comprises: a second conductive layer (54) disposed on a bottom surface of the build-up layer structure (see figure 1), wherein the second conductive layer (54) comprises a second ground plane (52) in contact with the first through via (56); and a second solder mask layer (64) disposed on the second conductive layer (54); wherein the second solder mask layer has a second opening to expose the first through via (as taught by Nakazawa).
Regarding claim 9, Kanbe discloses the electronic system (see figure 1), wherein the first conductive layer (54) comprises base pads comprising the ground pad (71), each of the base pads has a pad shape and a pad area (see figure 1), and the first through via (56) is interposed between the pads and has a first through via shape and a first through via area (see figure 1).
Regarding claim 10, Kanbe discloses the claimed invention except for the first through via shape being the same as the pad shape, and wherein the first through via area is greater than or same to the pad area. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first through via shape being the same as the pad shape, and wherein the first through via area being greater than or same to the pad area to improve heat dissipation. Furthermore, where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular shape, a change of shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), since such a modification would have involved a mere change in the shape of a component
Regarding claim 11, Kanbe discloses the claimed invention except for a shape of the first opening is different from the first through via shape. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first opening with a different shape from the first through via shape to improve heat dissipation. Furthermore, where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular shape, a change of shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), since such a modification would have involved a mere change in the shape of a component
Regarding claim 13, Kanbe discloses the electronic system (see figure 1), wherein the build-up layer structure (see figure 1) further comprises: a second through via (55) passing through the build-up layer structure (see figure 1) and located in the device-attach region, wherein the second through via (55) has a second through via area and a second through via shape (see figure 1).
5. Claims 12 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kanbe et al (JP 2000-101245; cited in the IDS; hereinafter Kanbe) in view of Nakazawa et al (US 9,474,166; hereinafter Nakazawa) as applied in claim 9, and further in view of Mahanta et al (US 9,795,026; hereinafter Mahanta).
Regarding claim 12, the modified Kanbe discloses the claimed invention except for the electronic system, wherein the through via shape comprises a circle, an oval, a criss-cross sign, the letter X, a line shape, or a combination thereof. Mahanta teaches thermal vias with a circle, an oval, a criss-cross sign, the letter X, a line shape or a combination thereof (see figures 5 and 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the electronic system, wherein the through via shape comprises a circle, an oval, a criss-cross sign, the letter X, a line shape, or a combination thereof as taught by Mahanta to improve heat dissipation.
Regarding claim 14, the modified Kanbe discloses the electronic device wherein the first solder mask layer (63) comprises a third opening (as taught by Nakazawa) to expose the second through via (55), wherein a first shape of the first opening corresponds to the first through via shape (56), and a second shape of the third opening (as taught by Nakazawa) corresponds to the second through via shape.
Regarding claim 15, Kanbe discloses the claimed invention except for the electronic system, wherein the first through via shape is different from the pad shape. It would have been an obvious matter of design choice to make the electronic system, wherein the first through via shape is different from the pad shape the through via shape to improve heat dissipation. Furthermore, where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular shape, a change of shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 16, Kanbe discloses the claimed invention except for the electronic system, wherein an area of the first opening is greater than twice an area of the pad. It would have been an obvious matter of design choice to make the electronic system, wherein an area of the first opening is greater than twice an area of the pad to improve heat dissipation. Furthermore, where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular shape, a change of shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 17, Kanbe discloses the claimed invention except for the electronic system, wherein the shape of the first opening is same as the shape of the first through via. It would have been an obvious matter of design choice to make the electronic system, wherein the shape of the first opening is same as the shape of the first through via to improve heat dissipation. Furthermore, where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular shape, a change of shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kasuya et al (US 8,022,532), Sathe (US 6,800,947), Figueroa et al (US 6,388,207), Berg et al (US 5,756,380), Taylor (US 5,3,90,078), Kawasaki et al (US 6,930,258), Naitoh et al (US 6,912,779), Takeuchi et al (US 6,894,888), Takano et al (US 6,891,732), Lim (US 9,198,278) and Seto (US 12,550,254) disclose an electronic system.
7. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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May 16, 2026
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
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