DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 8/24/2026. Claims 1-20 are pending in this application. Claims 1-6 & 15-20 are withdrawn.
Claims 7-14 are examined in this Office Action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 7-9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa et al. (US 2003/0015743).
Re claim 1, Ogawa teaches, under BRI, Fig. 1A, claim 11, [0020, 0048-0053], a memory device, comprising:
-a plurality of memory cells (in Rec region), each memory cell comprising:
at least one first transistor (TR);
a cell interconnection structure (20a, 30a, 32a) formed over the at least one first transistor and in electrical contact with the at least one first transistor (indicated), the cell interconnection structure (20a, 30a, 32a) comprising a cell plate (32a) disposed at a top layer of the cell interconnection structure (20a, 30a, 32a); and
at least one capacitor (MC) electrically coupled to the at least one first transistor (TR) through the cell interconnection structure (20a, 30a, 32a), each capacitor comprising:
a first electrode (35a);
a second electrode (33a) surrounding at least a portion (e.g., center) of the first electrode (35a), the second electrode electrically contacting the cell plate (32a); and
a ferroelectric layer (34a) disposed between the first electrode (35a) and the second electrode (33a); and
-a dummy memory cell (in Rdc region), comprising:
at least one second transistor (with gates 15 on insulating film 11 in Rdc region);
a first conductive layer (21b) disposed above the at least one second transistor (15); and
a first via structure (30b) disposed on the first conductive layer (21b),
wherein the first via structure (30b) is in electrical contact with the first electrode (35a) through a second conductive layer (36); and
wherein the first conductive layer (21b) is beneath the second conductive layer (36).
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Re claim 8, Ogawa teaches, Fig. 1A, wherein the first via structure (30b) overlaps the dummy memory cell (e.g., transistor in Rdc region) in a plan view of the memory device.
Re claim 9, Ogawa teaches, Fig. 1A, wherein the second conductive layer (36) is disposed on and in direct contact with the first electrode (35a).
Re claim 11, Ogawa teaches, Fig. 1A, wherein the cell plate (32a) and the first conductive layer (21b) are formed in a same manufacturing process (*).
(*) The limitation "formed in a same manufacturing process" is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Hu et al. (CN 111900170 A).
The teachings of Ogawa have been discussed above.
Re claim 10, Ogawa does not teach wherein the second conductive layer is disposed on and in electric contact with the first electrode through a second via structure.
Hu teaches, Fig. 3, the second conductive layer (361) is disposed on and in electric contact with the first electrode (of capacitor 340) through a second via structure (351).
As taught by Hu, one of ordinary skill in the art would utilize & modify the above teaching into Ogawa to obtain the second conductive layer is disposed on and in electric contact with the first electrode through a second via structure as claimed, because it aids in facilitating interconnection within the formed memory device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hu in combination Ogawa due to above reason.
4. Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Hayashi et al. (US 2003/0168686).
The teachings of Ogawa have been discussed above.
Re claim 12, Ogawa teaches, Fig. 1A, [0052], a periphery circuit (right region including Rdc) configured to control operations of the plurality of memory cells (in Rec region), comprising: a periphery interconnection structure (30c, 42), wherein a third conductive layer (42) of the periphery interconnection structure is in electric contact with the first conductive layer (21b).
Ogawa does not explicitly teach the peripheral circuit comprising: at least one third transistor; and the peripheral interconnect structure electrically coupled to the at least one third transistor.
Hayashi teaches, Fig. 1, [0005, 0006, 0009], the peripheral circuit (10B) comprising: at least one third transistor (with gate 13D); and the peripheral interconnect structure (15C, 21A above 13D) electrically coupled to the at least one third transistor.
As taught by Hayashi, one of ordinary skill in the art would utilize & modify the above teaching to obtain the peripheral circuit comprising: at least one third transistor; and the peripheral interconnect structure electrically coupled to the at least one third transistor as claimed, because it aids in achieving a completed memory device structure having improved speed/performance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hayashi in combination Ogawa due to above reason.
Re claim 13, Ogawa/Hayashi does not explicitly teach wherein top surfaces of the third conductive layer and the first conductive layer are flush with each other.
Hayashi teaches, Fig. 3C, [0082], top surfaces of conductive layers (37C, 37D) are flush with each other.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Hayashi to obtain top surfaces of the third conductive layer and the first conductive layer are flush with each other as claimed, because it aids in achieving desired arrangement of conductive layers within a peripheral region, and further it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Re claim 14, Ogawa teaches, under BRI, Fig. 1A, wherein the third conductive layer (42) and the first conductive layer (21b) are extended and directly connected (via 30c) to each other.
Response to Arguments
5. Applicant's arguments filed 8/24/2026 have been fully considered but they are not persuasive.
Applicant submits “Ogawa’s express description of the Rdc region does not support either aspect of the Office Actions’ mapping” & “Ogawa neither identifies the dummy cell region Rdc as a dummy memory cell nor identifies a transistor within that region”.
The examiner respectfully disagrees.
Claim 7 recites “a dummy memory cell, comprising: at least one second transistor”. Shown in Figs. 1A-B, gate electrodes 15 (isolated from others, shown under Rdc region), formed on insulating film 11, can be considered as claimed second transistor. Dummy cell region Rdc, next to memory cell region Rec, applied to indicate position/location of the transistor (see Figs. 1A-B). It is acknowledged that par. [0053] of Ogawa does not clearly describe a dummy memory cell, however it clearly shows that Ogawa teaches a dummy transistor (or dummy cell) in a DRAM memory cell. The claim does not require a full structural transistor, the dummy (structural) transistor taught by Ogawa, shown in Fig. 1A, under BRI, can be treated and considered as a transistor structure.
Further, a reference considered as a whole, in pars. [0114, 0134], Ogawa teaches a memory capacitor MC and a dummy cell provided on or across interlayer insulating film. Supported by Kanda (US 2014/0291748, [0084]) cites “The dummy cell (dummy transistor) DT1A has a substantial same structure as the memory cell MC”. Therefore, it is easily recognized by a skilled person in the art that the dummy (memory) cell taught by Ogawa includes at least one transistor.
For the above reason, and given a broadest reasonable interpretation, Ogawa teaches the claimed invention including “a dummy memory cell, comprising: at least one second transistor”.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ogawa (US 2006/0163639, Fig. 2A) discloses a semiconductor memory device includes a memory cell and a dummy cell.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/17/26
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