Prosecution Insights
Last updated: July 17, 2026
Application No. 18/596,068

NEURON CIRCUITS FOR A SPIKING NEURAL NETWORK BASED ON A VOLTAGE-CONTROLLED MAGNETIC-TUNNEL-JUNCTION LAYER STACK

Non-Final OA §103
Filed
Mar 05, 2024
Examiner
HOANG, TUAN A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
GlobalFoundries Singapore Pte. Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
377 granted / 510 resolved
+5.9% vs TC avg
Moderate +12% lift
Without
With
+11.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
27 currently pending
Career history
536
Total Applications
across all art units

Statute-Specific Performance

§103
86.7%
+46.7% vs TC avg
§102
5.4%
-34.6% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 510 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 2, and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. US 18/377844 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because Regarding claim 1, claim 1 of the reference application teaches a structure for a spiking neural network, the structure comprising: a first leaky-integrate-fire neuron (this is treated as a label of a circuit) including a first magnetic-tunneling-junction layer stack (claim 1 of reference application, lines 2); and a power source connected to the first magnetic-tunneling-junction layer stack, the power source configured to provide a plurality of voltage pulses to the first magnetic-tunneling-junction layer stack (claim 1 of reference application, lines 6-8). Regarding claim 2, claim 3 of the reference application teaches all limitations of the structure of claim 1 and also teaches wherein the first leaky-integrate-fire neuron includes an input coupled to the power source and an output (input is implicit structures), and the first magnetic-tunneling-junction layer stack includes a first electrode coupled to the input and a second electrode (MTJ structure has two electrodes) coupled to the output. Regarding claim 20, claim 20 teaches of the reference application teaches a method of forming a structure for a spiking neural network, the method comprising: forming a leaky-integrate-fire neuron (this is treated as a label of a circuit) including a magnetic-tunneling-junction layer stack (claim 1 of reference application, lines 2), wherein the magnetic-tunneling-junction layer stack is connected to a power source (claim 1 of reference application, lines 7-9), and the power source is configured to provide a plurality of voltage pulses to the magnetic-tunneling-junction layer stack . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2020/0117983 A1) in view of Katine et al. (US 2022/0223650 A1). Regarding claim 1, Lee teaches a structure for a spiking neural network (artificial neuron network device containing the artificial neuron device 100, as described in [0078] in Fig. 2A-2B of Lee), the structure comprising: a first leaky-integrate-fire neuron (100 in Fig. 2A-2B of Lee) including a first switching device stack (TS device); and a power source (the source that provides the voltage pulses in Fig. 5 and [0054] of Lee) connected to the first magnetic-tunneling-junction layer stack, the power source configured to provide a plurality of voltage pulses (pulses in Fig. 5) to the first switching device stack. But Lee does not teach that the first switching device stack is a magnetic-tunneling-junction layer stack (Lee discloses that the first switching device is an ovionic threshold switching device, [0011] of Lee). Katine teaches an MTJ device structure (array in Fig. 1-23C of Katine) that comprises an MTJ stack (180 in Fig. 2) including: a fixed magnetization layer (112 in Fig. 2); a reference layer (132); a tunnel barrier layer (134); a free layer (136) sandwiched between two electrodes (30 and 90L in Fig. 14B-C). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Katine’s MTJ structure as threshold switch device of Lee in order to obtain high scalability and integration, lower power consumption and high endurance and reliability. Regarding claim 2, Lee in view of Katine teaches all limitations of the structure of claim 1, and also teaches wherein the first leaky-integrate-fire neuron includes an input (node N1 in Fig. 2A-2B of Lee) coupled to the power source (as described in [0042] of Lee) and an output (node N2 in Fig. 2A-2B of Lee), and the first magnetic-tunneling-junction layer stack includes a first electrode (TE in Fig. 4 of Lee, which is analogous to 90 in Fig. 2 and 14C of Katine) coupled to the input and a second electrode (BE in Fig. 4 of Lee, which is analogous to 30) coupled to the output. Regarding claim 3, Lee in view of Katine teaches all limitations of the structure of claim 2 and also teaches wherein the first magnetic-tunneling-junction layer stack includes a free layer (136 in Fig. 2 of Katine) adjacent to the first electrode, a reference layer (132 in Fig. 2 of Katine) adjacent to the second electrode, and a tunnel barrier (134) layer between the reference layer and the free layer. Regarding claim 4, Lee in view of Katine teaches all limitations of the structure of claim 3 and also teaches wherein the first magnetic-tunneling-junction layer stack includes a synthetic antiferromagnetic pinning layer (112 in Fig. 2 of Katine) between the reference layer and the second electrode. Regarding claim 5, Lee in view of Katine teaches all limitations of the structure of claim 3 and also teaches wherein the tunnel barrier layer has a thickness in a range of 1 nanometer to 100 nanometers (as described in [0123] of Katine). Regarding claim 6, Lee in view of Katine teaches all limitations of the structure of claim 5 and also teaches wherein the first magnetic-tunneling-junction layer stack includes a synthetic antiferromagnetic pinning layer (112 in Fig. 2 of Katine) between the reference layer and the second electrode. Regarding claim 7, Lee in view of Katine teaches all limitations of the structure of claim 2 and further comprising: a capacitor (C in Fig. 2A of Lee) coupled to the input; and a resistor (R2 in Fig. 2A of Lee) coupled to the output. Regarding claim 8, Lee in view of Katine teaches all limitations of the structure of claim 7 and also teaches wherein the capacitor is coupled to the input in parallel with the first magnetic-tunneling-junction layer stack (as shown in Fig. 2A of Lee). Regarding claim 9, Lee in view of Katine teaches all limitations of the structure of claim 7 and also teaches wherein the resistor is coupled to the output in parallel with the first magnetic-tunneling-junction layer stack (as shown in Fig. 2A of Lee). Regarding claim 10, Lee in view of Katine teaches all limitations of the structure of claim 1 and also teaches wherein the first magnetic-tunneling-junction layer stack has a first threshold voltage (Vth in equation 4, as described in [0045] of Lee) for generating a first voltage spike (as shown in Fig. 5 of Lee). Regarding claim 11, Lee in view of Katine teaches all limitations of the structure of claim 10 and further comprising: a chip (1000 in Fig. 10 of Lee); and a second leaky-integrate-fire neuron including a second magnetic-tunneling-junction layer stack (artificial neuron circuit 1110 is identified as the first leaky-integrate-fire neuron, and 1120 is identified as the second one), wherein the first leaky-integrate-fire neuron and the second leaky-integrate-fire neuron are disposed on the chip (as shown in Fig. 10 of Lee). Regarding claim 12, Lee in view of Katine teaches all limitations of the structure of claim 11 and also teaches wherein the second magnetic-tunneling-junction layer stack includes a tunnel barrier layer (as combined in claim 1, each switching device of Lee is replaced with 180 of Katine. Thus, the second MTJ layer stack also has a tunnel barrier layer 134 in Fig. 2 of Katine), the tunnel barrier layer of the first magnetic-tunneling-junction layer stack has a first thickness (thickness of 134 of Katine), and the tunnel barrier layer of the second magnetic-tunneling-junction layer stack has a second thickness different from the first thickness (since the claim language does not specify how much different the thicknesses of the barrier layer 134 of Katine, thus, the inherent variation in thickness in manufacturing process of the barrier layer would satisfy this limitation). Regarding claim 13, Lee in view of Katine teaches all limitations of the structure of claim 12 and also teaches wherein the first thickness ranges from 1 nanometer to 100 nanometers (as described in [0123] of Katine), and the second thickness ranges from 1 nanometer to 100 nanometers (as described in [0123] of Katine). Regarding claim 16, Lee in view of Katine teaches all limitations of the structure of claim 1 and further comprising: a first wiring level (level of the top electrode TE in Fig. 4 of Lee) including a first interconnect (top electrode line TE); and a second wiring level (level of the bottom electrode BE in Fig. 4 of Lee) including a second interconnect, wherein the first magnetic-tunneling-junction layer stack is disposed between the first wiring level and the second wiring level (as shown in Fig. 4 of Lee). Regarding claim 17, Lee in view of Katine teaches all limitations of the structure of claim 1 and also teaches wherein the first magnetic-tunneling-junction layer stack includes a free layer (136 in Fig. 2 of Katine), a reference layer (132), and a tunnel barrier layer (134) between the reference layer and the free layer. Regarding claim 18, Lee in view of Katine teaches all limitations of the structure of claim 17 and also teaches wherein the first magnetic-tunneling-junction layer stack includes a synthetic antiferromagnetic pinning layer (112 in Fig. 2 of Katine), and the reference layer is disposed between the tunnel barrier layer and the synthetic antiferromagnetic pinning layer (as shown in Fig. 2 of Katine). Regarding claim 19, Lee in view of Katine teaches all limitations of the structure of claim 1 and also teaches wherein the power source is a power supply (2300 in Fig. 11 of Lee). Regarding claim 20, Lee teaches a method of forming a structure for a spiking neural network (circuit containing the artificial neuron device 100 in Fig. 2A-2B of Lee), the method comprising: forming a leaky-integrate-fire neuron (100 in Fig. 2A-2B of Lee) including a first switching device stack, wherein the first switching stack is connected to a power source (the source that provides the voltage pulses in Fig. 5 and [0054] of Lee), and the power source is configured to provide a plurality of voltage pulses (pulses in Fig. 5) to the first switching device stack. But Lee does not teach the first switching device stack is a magnetic-tunneling-junction layer stack (Lee discloses that the first switching device is an ovionic threshold switching device, [0011] of Lee). Katine teaches an MTJ device structure (array in Fig. 1-23C of Katine) that comprises an MTJ stack (180 in Fig. 2) including: a fixed magnetization layer (112 in Fig. 2); a reference layer (132); a tunnel barrier layer (134); a free layer (136) sandwiched between two electrodes (30 and 90L in Fig. 14B-C). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Katine’s MTJ structure as threshold switch device of Lee in order to obtain high scalability and integration, lower power consumption and high endurance and reliability. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Katine, as applied to claims 12, 11 above, and further in view of van Dal et al. (US 2020/0311524 A1). Regarding claim 14, Lee in view of Katine teaches all limitations of the structure of claim 12 and also teaches wherein the first magnetic-tunneling-junction layer stack has a first critical dimension (width of the MTJ stack of the neuron circuit 1110 of Lee-Katine), and the second magnetic-tunneling-junction layer stack has a second critical dimension (width of the MTJ stack of the neuron circuit 1120 of Lee-Katine). But Lee in view of Katine does not teach the second critical dimension is different from the first critical dimension. van Dal teaches a neuron circuit (Figs. 1A-1C of van Dal) comprising a first neuron element (128a in Figs. 1A-1C) and a second neuron element (128b); the neuron elements have different widths thus have different threshold voltages (as described in [0022] of van Dal). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first and second critical dimension to be different, as disclosed by van Dal, in order to increase the number of synaptic weight values in the circuit, thereby increasing accuracy and efficiency of the neural network (see [0022] of van Dal). Regarding claim 15, Lee in view of Katine teaches all limitations of the structure of claim 11 but does not teach wherein the second magnetic-tunneling-junction layer stack has a second threshold voltage for generating a second voltage spike, and the second threshold voltage differs from the first threshold voltage. van Dal teaches a neuron circuit (Figs. 1A-1C of van Dal) comprising a first neuron element (128a in Figs. 1A-1C) and a second neuron element (128b); the neuron elements have different widths thus have different threshold voltages (as described in [0022] of van Dal). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first and second critical dimension to be different, as disclosed by van Dal, in order to increase the number of synaptic weight values in the circuit, thereby increasing accuracy and efficiency of the neural network (see [0022] of van Dal). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Tuan A Hoang/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 05, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
85%
With Interview (+11.5%)
2y 8m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 510 resolved cases by this examiner. Grant probability derived from career allowance rate.

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