DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species A of Figs. 1-2 and Subspecies (a) of Fig. 3, claims 1-3, 6-7, 9-19, in the reply filed on July 27, 2026 is acknowledged. Examiner notes that claims 4-5 are directed to non-elected Subspecies, because claim 4 is directed to Subspecies (e) of Fig. 12, claims 8 and 20 are directed to non-elected Species, because the elected Species A does not include a transition pattern of claims 8 and 20, and claims 21-27 are directed to non-elected Species, because a transition pattern of claim 21 is directed to Species E of Figs. 15-16. Therefore, claims 1-3, 6-7 and 9-19 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, it is not clear how the second gate dielectric film and the second gate electrode can be sequentially stacked on the third bridge pattern and the fourth bridge pattern, when the first gate structure includes a second gate dielectric film and a second gate electrode, as recited on lines 1-2 of claim 16, because claim 12 recites “a first bridge pattern and a second bridge pattern that are sequentially stacked on the first region” (emphasis added, lines 3-4 of claim 12), whereas “a third bridge pattern and a fourth bridge pattern that are sequentially stacked on the second region” (emphasis added, lines 13-14 of claim 12). Claim 12 further recites “the first bridge pattern and the second bridge pattern extends through the first gate structure” (lines 7-8 of claim 12), thereby indicating that the first gate structure is associated with the first region. However, claim 16 recites that the first gate structure includes a second gate dielectric film and a second gate electrode that are sequentially stacked on the third bridge pattern and the fourth bridge pattern. Because the third bridge pattern and the fourth bridge pattern are located in the second region, it remains unclear how components of the first gate structure, which is associated with the first region, can be sequentially stacked on the third and fourth bridge patterns in the second region.
Claims 17-18 depend on claim 16, therefore, claims 17-18 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7 and 9-10 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Zhou et al. (US 2023/0411392, hereinafter Zhou).
Regarding claim 1, Zhou discloses a semiconductor device comprising:
a substrate (semiconductor substrate 10, Fig. 11A-B) including a first region (Fig. 11B) and a second region (Fig. 11A);
a first bridge pattern (lowest second semiconductor channel material nanosheet 14R, Fig. 11B) on the first region (Fig. 11B), the first bridge pattern (lowest 14R, Fig. 11B) extending in a first direction (lateral direction, Fig. 11B) and spaced apart from the substrate (10, Fig. 11B), and the first bridge pattern (lowest 14R, Fig. 11B) having a first width (width of 14R, Fig. 11B);
a first gate structure (second gate region 32R/34R, Fig. 11B) extending in a second direction (page in and out direction, Fig. 11B), wherein the second direction (page in and out direction, Fig. 11B) intersects the first direction (lateral direction, Fig. 11B), and the first bridge pattern (lowest 14R, Fig. 11B) extends through the first gate structure (32R/34R, Fig. 11B);
first epitaxial patterns (second source/drain region 28R, Fig. 11B) connected to the first bridge pattern (lowest 14R, Fig. 11B) on side surfaces of the first gate structure ((indirectly) on side surfaces of 32R/34R, Fig. 11B);
first inner spacers (second inner spacers 26R, Fig. 11B) interposed between the substrate (10, Fig. 11B) and the first bridge pattern (lowest 14R, Fig. 11B) and between the first gate structure (32R/34R, Fig. 11B) and the first epitaxial patterns (28R, Fig. 11B);
a second bridge pattern (lowest first semiconductor channel material nanosheet 14L, Fig. 11A) extending in the first direction (lateral direction, Fig. 11A) on the second region (Fig. 11A), the second bridge pattern (lowest 14L, Fig. 11A) spaced apart from the substrate (10, Fig. 11A), the second bridge pattern (lowest 14L, Fig. 11A) having a second width (width of 14L, Fig. 11A), and the second width (width of 14L, Fig. 11A) being greater than the first width (width of 14R, Fig. 11B);
a second gate structure (first gate region 32L/34L, Fig. 11A) extending in the second direction (page in and out direction, Fig. 11A), wherein the second bridge pattern (lowest 14L, Fig. 11A) extends through the second gate structure (32L/34L, Fig. 11A);
second epitaxial patterns (first source/drain region 28L, Fig. 11A) connected to the second bridge pattern (lowest 14L, Fig. 11A) on side surfaces of the second gate structure ((indirectly) on side surfaces of 32L/34L, Fig. 11A); and
second inner spacers (first inner spacers 26L, Fig. 11A) interposed between the substrate (10, Fig. 11A) and the second bridge pattern (lowest 14L, Fig. 11A) and between the second gate structure (32L/34L, Fig. 11A) and the second epitaxial patterns (28L, Fig. 11A).
Regarding claim 7, Zhou further discloses for the semiconductor device of claim 1 that the first epitaxial patterns (28R, Fig. 11B) are in contact with the first inner spacers (26R, Fig. 11B), and the second epitaxial patterns (28L, Fig. 11A) are in contact with the second inner spacers (26L, Fig. 11A).
Regarding claim 9, Zhou further discloses for the semiconductor device of claim 1, further comprising that
a third bridge pattern (middle 14R, Fig. 11B), wherein the third bridge pattern (middle 14R, Fig. 11B) is further away from the substrate (10, Fig. 11B) than the first bridge pattern (lowest 14R, Fig. 11B) on the first region (Fig. 11B), and the third bridge pattern (middle 14R, Fig. 11B) extends through the first gate structure (32R/34R, Fig. 11B) in the first direction (lateral direction, Fig. 11B); and
a fourth bridge pattern (middle 14L, Fig. 11A), wherein the fourth bridge pattern (middle 14L, Fig. 11A) is further away from the substrate (10, Fig. 11A) than the second bridge pattern (lowest 14L, Fig. 11A) on the second region (Fig. 11A), and the fourth bridge pattern (middle 14L, Fig. 11A) extends through the second gate structure (32L/34L, Fig. 11A) in the first direction (lateral direction, Fig. 11A).
Regarding claim 10, Zhou further discloses for the semiconductor device of claim 9 that the first inner spacers (26R, Fig. 11B) are interposed between the first bridge pattern (lowest 14R, Fig. 11B) and third bridge pattern (middle 14R, Fig. 11B), and the second inner spacers (26L, Fig. 11A) are interposed between the second bridge pattern (lowest 14L, Fig. 11A) and fourth bridge pattern (middle 14L, Fig. 11A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhou et al. (US 2023/0411392, hereinafter Zhou) in view of Kim et al. (KR 20170097322, hereinafter Kim).
Regarding claim 2, Zhou does not explicitly disclose that a first thickness of the first inner spacers in the first direction is greater than a second thickness of the second inner spacers in the first direction.
However, Kim discloses a gate-all-around transistor structure including first and second transistor regions (left and right regions, Fig. 2), and the first transistor region (left region, Fig. 2) includes the gate electrode 120 having the width G11, while the second transistor region (right region, Fig. 2) includes the gate electrode 220 with the width G21, and the width G11 is greater than the width G21 (Fig. 2). Kim further discloses that the corresponding first inner spacers 142 have a spacer width SW11 that is smaller than the spacer width of SW21 of the second inner spacers 242. Therefore, Kim teaches that the dimensions of the inner spacers are selected in accordance with the corresponding gate structure, such that a narrow gate is provided with a wider spacer and a wider gate is provided with a narrower inner spacer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate-all-around FET structure of Zhou in view of Kim by selecting different inner spacer widths for different transistor regions according to the corresponding gate dimensions, as taught by Kim, in order to improve electrical isolation and optimize the device performance of the gate-all-around FETs.
Regarding claim 11, Zhou further discloses that the first width (second lateral width W2, Fig. 1A-B) is 5 nm to 20 nm, and the second width (first lateral width W1, Fig. 1A-B) is 20 nm to 100 nm, because “the first sacrificial semiconductor material nanosheets 12L and the first semiconductor channel material nanosheets 14L have a first lateral width, i.e., W1 shown in FIG. 1A, from 25 nm to 200 nm, while the second sacrificial semiconductor material nanosheets 12R and the second semiconductor channel material nanosheets 14R have a second lateral width, i.e., W2 shown in FIG. 1B, from 3 nm to 25 nm” (emphasis added, [0053]).
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 2023/0411392, hereinafter Zhou) in view of Yeong et al (US 2021/0202758, hereinafter Yeong).
Regarding claim 3, Zhou differs from the claimed invention by not showing that inner side surfaces of the first inner spacers that are opposite to the first gate structure include concave surfaces, and inner side surfaces of the second inner spacers that are opposite to the second gate structure include concave surfaces.
However, Yeong discloses a gate-all-around FET device including the inner spaces 131 having concave side surfaces that are opposite to the gate stack 123 (Figs. 16-19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner spacers of Zhou to include the concave side surfaces taught by Yeong as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Regarding claim 6, Zhou differs from the claimed invention by not showing that outer side surfaces of the first inner spacers that are opposite to the first epitaxial patterns include concave surfaces, and outer side surfaces of the second inner spacers that are opposite to the second epitaxial patterns include concave surfaces.
However, Yeong discloses a gate-all-around FET device including the inner spaces 131 having concave side surfaces that are opposite to the gate stack 123 (Figs. 16-19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner spacers of Zhou to include the concave side surfaces taught by Yeong as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhou et al. (US 2023/0411392, hereinafter Zhou) in view of Liaw (US 2020/0343387).
Regarding claim 12, Zhou further discloses a semiconductor device comprising:
a substrate (10, Fig. 11A-B) including a first region (Fig. 11B) and a second region (Fig. 11A);
a first bridge pattern (lowest 14R, Fig. 11B) and a second bridge pattern (middle 14R, Fig. 11B) that are sequentially stacked on the first region (Fig. 11B), the first bridge pattern (lowest 14R, Fig. 11B) and the second bridge pattern (middle 14R, Fig. 11B) extending in a first direction (lateral direction, Fig. 11B) and spaced apart from the substrate (10, Fig. 11B);
a first gate structure (second gate region 32R/34R, Fig. 11B) extending in a second direction (page in and out direction, Fig. 11B), wherein the second direction (page in and out direction, Fig. 11B) intersects the first direction (lateral direction, Fig. 11B), and the first bridge pattern (lowest 14R, Fig. 11B) and the second bridge pattern (middle 14R, Fig. 11B) extends through the first gate structure (32R/34R, Fig. 11B);
first inner spacers (26R, Fig. 11B) on side surfaces of the first gate structure (side surface of 32R/34R, Fig. 11B) and between the first bridge pattern (lowest 14R, Fig. 11B) and the second bridge pattern (middle 14R, Fig. 11B);
first epitaxial patterns (second source/drain region 28R, Fig. 11B) connected to the first bridge pattern (lowest 14R, Fig. 11B) and the second bridge pattern (middle 14R, Fig. 11B) on outer side surfaces of the first inner spacers (side surfaces of 26R, Fig. 11B);
a third bridge pattern (lowest 14L, Fig. 11A) and a fourth bridge pattern (middle 14L, Fig. 11A) that are sequentially stacked on the second region (Fig. 11A), the third and fourth bridge patterns (lowest 14L and middle 14L, Fig. 11A) extending in the first direction (lateral direction, Fig. 11A);
a second gate structure (32L/34L, Fig. 11A) extending in the second direction (page in and out direction, Fig. 11A), wherein the third bridge pattern (lowest 14L, Fig. 11A) and the fourth bridge pattern (middle 14L, Fig. 11A) extends through the second gate structure (32L/34L, Fig. 11A);
second inner spacers (26L, Fig. 11A) disposed on side surfaces of the second gate structure (side surfaces of 32L/34L, Fig. 11A) and between the third bridge pattern (lowest 14L, Fig. 11A) and the fourth bridge pattern (middle 14L, Fig. 11A); and
second epitaxial patterns (28L, Fig. 11A) connected to the third bridge pattern (lowest 14L, Fig. 11A) and the fourth bridge pattern (middle 14L, Fig. 11A) on outer side surfaces of the second inner spacers (26L, Fig. 11A),
and wherein a first thickness (lateral thickness or width of 14R, Fig. 11B) of the first inner spacers (14R, Fig. 11B) in the first direction (lateral direction, Fig. 11B) is greater than a second thickness (lateral thickness or width of 14L, Fig. 11A) of the second inner spacers (11L, Fig. 11A) in the first direction (lateral direction, Fig. 11A).
Zhou does not explicitly disclose that a first width of the first bridge pattern and the second bridge pattern in the second direction is less than a second width of the third bridge pattern and the fourth bridge pattern in the second direction.
However, Liaw discloses gate-all-around FETs including GAA nanosheet devices 140 and GAA nanowire devices 120 adjacent to each other (Fig. 7), which corresponds to the claimed second and first regions, respectively. Liaw further discloses that the vertically stacked multiple channels 122, which corresponds to the claimed first and second bridge patterns, have the width W2 and the vertically stacked multiple channels 142, which corresponds to the claimed third and fourth bridge patterns, have the width W1, and the width W2 is less than the width W1 in Y-direction (or column or width direction, Fig. 7)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the width of the nanosheet channel in Zhou’s device with the geometrical relationship taught by Liaw, as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Regarding claim 19, Zhou discloses that the first inner spacers (26R, Fig. 11B) and the second inner spacers (26L, Fig. 11A) include an oxide, because “each first inner spacer 26L is composed of a first inner spacer dielectric material such as, for example, silicon dioxide or silicon nitride” (emphasis added, [0065]).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhou et al. (US 2023/0411392, hereinafter Zhou) in view of Liaw (US 2020/0343387) as applied to claim 12, and further in view of Yeong et al (US 2021/0202758, hereinafter Yeong).
Regarding claim 13, Zhou in view of Liaw differs from the claimed invention by not showing that the first thickness of the first inner spacers decreases to a point and, from the point, increases along a direction away from the first bridge pattern.
However, Yeong discloses a gate-all-around FET device including the inner spaces 131 having concave left and right side surfaces, therefore, the lateral thickness, which corresponds to the claimed first thickness, decreases to a central point, and increases from the central point along a vertical direction away from the nanosheet 54 (Figs. 16-19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner spacers of Zhou and Liaw to include the concave side surfaces taught by Yeong as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Regarding claim 14, Zhou in view of Liaw differs from the claimed invention by not showing that inner side surfaces of the first inner spacers that are opposite to the first gate structure include concave surfaces.
However, Yeong discloses a gate-all-around FET device including the inner spaces 131 having concave side surfaces that are opposite to the gate stack 123 (Figs. 16-19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner spacers of Zhou to include the concave side surfaces taught by Yeong as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Regarding claim 15, Zhou in view of Liaw differs from the claimed invention by not showing that outer side surfaces of the first inner spacers that are opposite to the first epitaxial patterns include concave surfaces.
However, Yeong discloses a gate-all-around FET device including the inner spaces 131 having concave side surfaces that are opposite to the gate stack 123 (Figs. 16-19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner spacers of Zhou to include the concave side surfaces taught by Yeong as an alternative configuration, in order to improve device performance of the gate-all-around FET devices.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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