DETAILED ACTION
This office action is in response to the remarks filed on 09/08/2026.
Currently claims 1-15 are pending in the application. Claims 10-15 are withdrawn from consideration as being directed to a non-elected invention. No claim was amended in the reply filed on 09/08/2026. Claims 1-9 are examined in this Office action.
Response to Arguments
Applicant's arguments filed 09/08/2026 have been fully considered but they are not persuasive.
At the outset, the Remarks refer to "the Chen reference." The reference of record is US 2011/0285023 A1, whose first-named inventor is Wen-Wei Shen (Chen-Shien Chen and Ming-Fa Chen are co-inventors), and which is referred to as Shen in the Office action. The arguments are treated as directed to Shen. The Remarks also restate the rejection of claims 1, 4-5 and 9 twice; the second rejection of record is the rejection of claims 2-3 over Shen, Otremba and Heinrich, and further in view of Lim. No separate argument is presented for dependent claims 2-5 and 9, or against Otremba, Heinrich or Lim.
(a) Substrate 1206 (Fig. 12) and second substrate 1050 (Fig. 10) of Shen
Applicant argues (Remarks, pp. 6-7) that the Office action found substrate 1206 of Fig. 12 and second substrate 1050 of Fig. 10 "interchangeable," whereas Shen associates substrate 1206 with the interconnect structure of width W1, i.e., the first interconnect structure 1001 of substrate 100/1000, and not the second interconnect structure 1051 of second substrate 1050 (citing Shen [0041] - [0042], [0045], [0047]).
The argument is not persuasive. Claim 1 is rejected under 35 U.S.C. 103, not 35 U.S.C. 102. A reference is prior art for all that it teaches, including alternative embodiments, and a single reference may be relied upon for teachings drawn from different figures where, as here, they describe one system. MPEP 2123; In re Mouttet, 686 F.3d 1322, 1331 (Fed. Cir. 2012); Merck & Co. v. Biocraft Labs., Inc., 874 F.2d 804, 807 (Fed. Cir. 1989). Shen Figs. 10 and 12 describe one interconnection scheme: Fig. 10 shows the two mating interconnect structures, second substrate 1050 being "a substrate to be attached to the first substrate 1000 via a second interconnect structure 1051" (Shen Fig. 10; [0041]-[0042]), and Fig. 12 applies that same substrate-to-substrate interconnection to a vertical stack of a substrate 1206, a second integrated circuit die 1204, and a first integrated circuit die 1202 (Shen Fig. 12; [0044]-[0045]). Shen further teaches that each of its substrates may be an integrated circuit die, an interposer, a packaging substrate or a printed circuit board (Shen [00xx]). The Office action relied on Fig. 12 for the claimed sequence (substrate layer stack, first semiconductor layer stack thereon, second semiconductor layer stack thereon) and on Fig. 10 for the metallization of a substrate-side interconnect. The designation "1206/1050" identifies the substrate as shown in those two views; it is not a finding that requires the two figures to be bodily identical.
Applicant's observation that Shen assigns the narrower W1 structure to substrate 1206 ([0047]) does not change the result. Shen's W1/W2 assignment concerns the relative widths of the mating interconnects and places the wider W2 structure on the side of the extremely low-k (ELK) film 1210 to reduce joint stress (Shen Fig. 12; [0047]). Claim 1 recites no interconnect width and no width relationship, so which mating structure the substrate carries is immaterial to claim 1. Moreover, on Applicant's own reading, substrate 1206 carries the first interconnect structure 1001 of substrate 100/1000, which includes conductive pads 102 of copper "provided in an upper surface of the substrate 100" (Shen Fig. 1; [0020]). Thus substrate 1206 has a metallic upper surface under either reading of Shen.
(b) "a substrate with a metallic upper surface"
Applicant argues (Remarks, p. 7) that the region annotated "metallic upper surface" on Shen Fig. 10 is a stack of layers (seed layer 858, conductive pad 856, seed layer 862) formed on first passivation layer 854 and not the upper surface of second substrate 1050, that Shen does not explicitly teach that substrate 1050 or 1206 has a metallic upper surface, and that Shen does not describe the structure between substrate 1206 and ELK film 1210.
The argument is not persuasive. During examination, claims are given their broadest reasonable interpretation consistent with the specification. MPEP 2111. Claim 1 recites "a substrate with a metallic upper surface"; it does not require that the metallic surface be the surface of a monolithic or bulk body, and it does not exclude dielectric or metal layers that form part of the substrate. Applicant's own specification describes the substrate as including, e.g., a direct bonded copper (DCB), active metal braze (AMB) or insulated metal substrate (IMS), or "a copper layer deposited on SiO2 substrate" (specification [0031], [0047]; claim 9), i.e., layered structures in which a deposited metal layer over an insulator provides the metallic upper surface. Shen describes its second substrate in the same way: the second substrate 850 "comprises a first passivation layer 854" and a conductive pad 856 formed over the first passivation layer 854 (Shen Fig. 8; [0036]), and second substrate 1050 is formed similarly to substrate 850 (Shen Fig. 10; [0041] - [0042]). The passivation layer 854, conductive pad 856 and seed layers 858, 862 are therefore part of the substrate as Shen itself describes it, and the uppermost metal of that substrate is its metallic upper surface. As to substrate 1206, Shen teaches that it may be a printed circuit board, an interposer, a laminate substrate, a packaging substrate, or a third integrated circuit die (Shen Fig. 12; [0045]), and, per Applicant, it carries the first interconnect structure of substrate 100 with its copper conductive pads 102 at the upper surface (see (a) above). The structure between substrate 1206 and ELK film 1210 is not recited in claim 1, which uses the open transition "comprising" (MPEP 2111.03).
In addition, the rejection does not rely on Shen alone for the substrate layer stack. Heinrich was relied upon for a substrate with a metallic upper surface having a Ni-containing layer thereon and a Sn-based solder layer over it for diffusion soldering: substrate 202 (leadframe; Heinrich Figs. 2A-2D; [0037]-[0043]) having a metal die attach region 208 that may comprise Cu, Ni and/or Ag, Ni-containing finishes such as Ni, NiV, NiP, NiP/Pd and NiP/Pd/Au, and a Sn-based solder preform 204 (Heinrich Figs. 2A-2D; [0037]-[0043]). One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In re Keller, 642 F.2d 413, 426 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986); MPEP 2145(IV).
(c) "a first Ni containing layer disposed on the substrate"
Applicant argues (Remarks, p. 8) that finish layer 1002 is formed directly on conductive pillar 864, which is separated from second substrate 1050 by several layers, and therefore is not "disposed on the substrate."
The argument is not persuasive. Claim 1 recites "a first Ni containing layer disposed on the substrate"; it does not recite "directly on" or "in contact with." Under the broadest reasonable interpretation, "on" encompasses over, with intervening layers, and the open transition "comprising" does not exclude the intervening layers (MPEP 2111, 2111.03). Applicant's claim 1 itself uses "on" for layers of a stack that are joined through further layers. Finish layer 1002 includes a nickel layer (Shen Fig. 10; [0043]) and is part of the second interconnect structure 1051 formed over second substrate 1050 (Shen Fig. 10; [0041] - [0043]); it is therefore disposed on the substrate. Further, Heinrich teaches the Ni-containing layer on the substrate metallization with the Sn-based solder thereon (Heinrich Figs. 2A-2D; [0037] - [0043]), as set forth in the rejection, and that teaching is not addressed in the Remarks. See In re Keller, supra.
For at least the reasons above, the rejection of claim 1, and of dependent claims 2-5 and 9 for which no separate argument was presented, is maintained. The grounds of rejection set forth below are the same as those in the Office action mailed 06/29/2026; no new ground of rejection is presented. Claims 6-8 remain objected to as set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0285023 A1 (Shen) and further in view of US 2007/0181908 A1 (Otremba) and US 2021/0143120 A1 (Heinrich).
Regarding claim 1, Shen discloses, a method for fabricating a semiconductor device, the method comprising:
PNG
media_image1.png
298
720
media_image1.png
Greyscale
providing a substrate layer stack (as annotated on Fig. 12; [0044]) comprising a substrate (1206/1050; Figs 10 and 12) with a metallic upper surface (as annotated on Fig. 10; [0037] – [0042]),
PNG
media_image2.png
646
468
media_image2.png
Greyscale
a first Ni containing layer (1002; finish layer; Fig. 10; [0043]) disposed on the substrate (1206/1050),
depositing a first semiconductor layer stack (1204; second integrated circuit die; Fig. 12; [0044]) on substrate layer stack;
depositing a second semiconductor layer stack (1202; first integrated circuit die; Fig. 12; [0044]) on the first semiconductor layer stack (1204),
connecting the first semiconductor layer stack (1204) to the substrate (1206) and the second semiconductor layer stack (1202) to the first semiconductor layer stack (1204) (Fig. 12; [0044])
But Shen fails to teach explicitly, performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack; providing a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer;
However, in analogous art, Otremba discloses, performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack (as annotated on Fig. 2; [0041] – [0043]);
PNG
media_image3.png
629
807
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen and Otremba before him/her, to modify the teachings of a semiconductor device using semiconductor layer stack as taught by Shen and to include the teachings of using diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack as taught by Otremba since by performing a diffusion soldering process, the problems associated with soft solder bonding, in particular, movement of the semiconductor components during subsequent die attach steps, are avoided ([0043]) and absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Otremba while forming a semiconductor device of Shen.
But the combination of Shen and Otremba fails to teach explicitly, the details of the process - providing a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer;
However, in analogous art, Heinrich discloses that in order to preform diffusion soldering for semiconductor die attach, a substrate with a metallic upper surface having a Ni-containing layer (Ni, NiV, NiP, etc.) disposed thereon, with a Sn-based solder preform positioned above it (Fig. 2; [0037] – [0043]). A semiconductor die whose back-metal is plated with NiP (or NiP/Pd, NiP/Pd/Au) to serve as the diffusion barrier and bonding layer. Applied to both faces of the first die (as required by the sandwich NiP/die/NiP structure of Claim 1), this is a straightforward extension since the frontside metal of the die also requires an interface metallization for bonding to the next layer (Fig. 2; [0037] – [0043]).
PNG
media_image4.png
220
684
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba and Heinrich before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the details of the diffusion soldering process as taught by Heinrich and modify the process to incorporate “to provide a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer”. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Heinrich while forming a semiconductor device of Shen.
Regarding claim 4, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein the first semiconductor layer stack further comprises a first Pd layer disposed on the first NiP layer on a side remote from the first semiconductor die, and a second Pd layer disposed on the second NiP layer on a side remote from the first semiconductor die (Fig. 2A; [0038]; Heinrich explicitly discloses Pd layers as optional additions to NiP die metallizations, teaching NiP/Pd and NiP/Pd/Au as standard variants of the die backside metallization. The purpose of Pd is to improve wettability of the NiP surface for the Sn-based solder and to act as a supplemental diffusion barrier). Therefore, it would be well within the purview of a person with ordinary skill in the art to add a Pd layer disposed on the first NiP layer on a side remote from the first semiconductor die.
Regarding claim 5, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein one or both of the first and second Ni containing layers comprise a Ni layer or a NiV layer ([0043]; Heinrich Ref.).
Note: Heinrich recites Ni and NiV as specific implementations of the generic “Ni-containing layer” used in die attach. Both Ni and NiV (nickel-vanadium alloy, used for its improved hardness and resistance to stress cracking) are conventional choices in diffusion soldering metallization. Their selection over other Ni-containing alloys is a routine engineering optimization with no unexpected result.
Regarding claim 9, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein the substrate (202; Fig. 2A) is one or more of a leadframe, a direct bonded copper (DCB), and active metal braze (AMB), an insulated metal substrate (IMS), or a copper layer deposited on SiO2 substrate (leadframe; [0038]; Heinrich Ref.).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Shen, Otremba and Heinrich as applied to claim 1 and further in view of US 2008/0224285 A1 (Lim).
Regarding claim 2, the combination of Shen, Otremba and Heinrich fails to teach explicitly, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor diode layer stack, wherein the first semiconductor die is a semiconductor diode die, wherein the second semiconductor layer stack is a semiconductor transistor layer stack, and wherein the second semiconductor die is a semiconductor transistor die.
However, in analogous art, Lim discloses, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor diode layer stack (150; control device having diodes; Fig. 3; [0056]), wherein the first semiconductor die is a semiconductor diode die (diode die), wherein the second semiconductor layer stack is a semiconductor transistor layer stack (120; power device having IGBT/transistors; Fig. 3; [0056]), and wherein the second semiconductor die is a semiconductor transistor die (transistor die).
Note: The arrangement of chips whether one is above the other or below the other is arbitrary as flipping the chip would satisfy the claim limitation.
PNG
media_image5.png
602
614
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba, Heinrich and Lim before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the chips contain diode and/or transistors as taught by Lim since in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The arrangement of chips whether one is above the other or below the other is obvious and it is well within the purview of a person with ordinary skill in the art. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming a semiconductor device of Shen.
Regarding claim 3, the combination of Shen, Otremba and Heinrich fails to teach explicitly, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor transistor layer stack, wherein the first semiconductor die is a semiconductor transistor die, wherein the second semiconductor layer stack is a semiconductor diode layer stack, and wherein the second semiconductor die is a semiconductor diode die.
However, in analogous art, Lim discloses, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor transistor layer stack (120; power device having IGBT/transistors; Fig. 3; [0056]), wherein the first semiconductor die is a semiconductor transistor die, wherein the second semiconductor layer stack is a semiconductor diode layer stack (150; control device having diodes; Fig. 3; [0056]), and wherein the second semiconductor die is a semiconductor diode die.
PNG
media_image5.png
602
614
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba, Heinrich and Lim before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the chips contain diode and/or transistors as taught by Lim since in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The arrangement of chips whether one is above the other or below the other is obvious and it is well within the purview of a person with ordinary skill in the art. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming a semiconductor device of Shen.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second Ni containing layers is in a range from 300 nm to 500 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second Ni containing layers is in a range from 300 nm to 500 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Regarding claim 7, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second Sn layers is in a range from 1100 nm to 1600 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second Sn layers is in a range from 1100 nm to 1600 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Regarding claim 8, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second NiP layers is in a range from 200 nm to 500 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second NiP layers is in a range from 200 nm to 500 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2020/0321499 A1 (Satou) - A bonding structure is disclosed that bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.
US 2011/0024881 A1 (Bhagath) - A semiconductor device is disclosed including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack.
US 2007/0205253 A1 (Hubner) - A method is disclosed for connecting at least two metal layers by means of a diffusion soldering process, wherein each of the metal layers that is to be connected is plated with a respective solder layer prior to the diffusion soldering process.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/12/2026
Prosecution Insights