DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Election/Restriction filed on 06/01/2026.
Currently claims 1-15 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-9, in the reply filed on 06/01/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0285023 A1 (Shen) and further in view of US 2007/0181908 A1 (Otremba) and US 2021/0143120 A1 (Heinrich).
Regarding claim 1, Shen discloses, a method for fabricating a semiconductor device, the method comprising:
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providing a substrate layer stack (as annotated on Fig. 12; [0044]) comprising a substrate (1206/1050; Figs 10 and 12) with a metallic upper surface (as annotated on Fig. 10; [0037] – [0042]),
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a first Ni containing layer (1002; finish layer; Fig. 10; [0043]) disposed on the substrate (1206/1050),
depositing a first semiconductor layer stack (1204; second integrated circuit die; Fig. 12; [0044]) on substrate layer stack;
depositing a second semiconductor layer stack (1202; first integrated circuit die; Fig. 12; [0044]) on the first semiconductor layer stack (1204),
connecting the first semiconductor layer stack (1204) to the substrate (1206) and the second semiconductor layer stack (1202) to the first semiconductor layer stack (1204) (Fig. 12; [0044])
But Shen fails to teach explicitly, performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack; providing a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer;
However, in analogous art, Otremba discloses, performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack (as annotated on Fig. 2; [0041] – [0043]);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen and Otremba before him/her, to modify the teachings of a semiconductor device using semiconductor layer stack as taught by Shen and to include the teachings of using diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack as taught by Otremba since by performing a diffusion soldering process, the problems associated with soft solder bonding, in particular, movement of the semiconductor components during subsequent die attach steps, are avoided ([0043]) and absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Otremba while forming a semiconductor device of Shen.
But the combination of Shen and Otremba fails to teach explicitly, the details of the process - providing a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer;
However, in analogous art, Heinrich discloses that in order to preform diffusion soldering for semiconductor die attach, a substrate with a metallic upper surface having a Ni-containing layer (Ni, NiV, NiP, etc.) disposed thereon, with a Sn-based solder preform positioned above it (Fig. 2; [0037] – [0043]). A semiconductor die whose back-metal is plated with NiP (or NiP/Pd, NiP/Pd/Au) to serve as the diffusion barrier and bonding layer. Applied to both faces of the first die (as required by the sandwich NiP/die/NiP structure of Claim 1), this is a straightforward extension since the frontside metal of the die also requires an interface metallization for bonding to the next layer (Fig. 2; [0037] – [0043]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba and Heinrich before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the details of the diffusion soldering process as taught by Heinrich and modify the process to incorporate “to provide a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer”. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Heinrich while forming a semiconductor device of Shen.
Regarding claim 4, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein the first semiconductor layer stack further comprises a first Pd layer disposed on the first NiP layer on a side remote from the first semiconductor die, and a second Pd layer disposed on the second NiP layer on a side remote from the first semiconductor die (Fig. 2A; [0038]; Heinrich explicitly discloses Pd layers as optional additions to NiP die metallizations, teaching NiP/Pd and NiP/Pd/Au as standard variants of the die backside metallization. The purpose of Pd is to improve wettability of the NiP surface for the Sn-based solder and to act as a supplemental diffusion barrier). Therefore, it would be well within the purview of a person with ordinary skill in the art to add a Pd layer disposed on the first NiP layer on a side remote from the first semiconductor die.
Regarding claim 5, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein one or both of the first and second Ni containing layers comprise a Ni layer or a NiV layer ([0043]; Heinrich Ref.).
Note: Heinrich recites Ni and NiV as specific implementations of the generic “Ni-containing layer” used in die attach. Both Ni and NiV (nickel-vanadium alloy, used for its improved hardness and resistance to stress cracking) are conventional choices in diffusion soldering metallization. Their selection over other Ni-containing alloys is a routine engineering optimization with no unexpected result.
Regarding claim 9, the combination of Shen, Otremba and Heinrich discloses, the method of claim 1, wherein the substrate (202; Fig. 2A) is one or more of a leadframe, a direct bonded copper (DCB), and active metal braze (AMB), an insulated metal substrate (IMS), or a copper layer deposited on SiO2 substrate (leadframe; [0038]; Heinrich Ref.).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Shen, Otremba and Heinrich as applied to claim 1 and further in view of US 2008/0224285 A1 (Lim).
Regarding claim 2, the combination of Shen, Otremba and Heinrich fails to teach explicitly, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor diode layer stack, wherein the first semiconductor die is a semiconductor diode die, wherein the second semiconductor layer stack is a semiconductor transistor layer stack, and wherein the second semiconductor die is a semiconductor transistor die.
However, in analogous art, Lim discloses, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor diode layer stack (150; control device having diodes; Fig. 3; [0056]), wherein the first semiconductor die is a semiconductor diode die (diode die), wherein the second semiconductor layer stack is a semiconductor transistor layer stack (120; power device having IGBT/transistors; Fig. 3; [0056]), and wherein the second semiconductor die is a semiconductor transistor die (transistor die).
Note: The arrangement of chips whether one is above the other or below the other is arbitrary as flipping the chip would satisfy the claim limitation.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba, Heinrich and Lim before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the chips contain diode and/or transistors as taught by Lim since in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The arrangement of chips whether one is above the other or below the other is obvious and it is well within the purview of a person with ordinary skill in the art. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming a semiconductor device of Shen.
Regarding claim 3, the combination of Shen, Otremba and Heinrich fails to teach explicitly, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor transistor layer stack, wherein the first semiconductor die is a semiconductor transistor die, wherein the second semiconductor layer stack is a semiconductor diode layer stack, and wherein the second semiconductor die is a semiconductor diode die.
However, in analogous art, Lim discloses, the method of claim 1, wherein the first semiconductor layer stack is a semiconductor transistor layer stack (120; power device having IGBT/transistors; Fig. 3; [0056]), wherein the first semiconductor die is a semiconductor transistor die, wherein the second semiconductor layer stack is a semiconductor diode layer stack (150; control device having diodes; Fig. 3; [0056]), and wherein the second semiconductor die is a semiconductor diode die.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shen, Otremba, Heinrich and Lim before him/her, to modify the teachings of a semiconductor device using stacking as taught by Shen and to include the teachings of the chips contain diode and/or transistors as taught by Lim since in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The arrangement of chips whether one is above the other or below the other is obvious and it is well within the purview of a person with ordinary skill in the art. Absent this important teaching in Shen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming a semiconductor device of Shen.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second Ni containing layers is in a range from 300 nm to 500 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second Ni containing layers is in a range from 300 nm to 500 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Regarding claim 7, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second Sn layers is in a range from 1100 nm to 1600 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second Sn layers is in a range from 1100 nm to 1600 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Regarding claim 8, the closest prior art, US 2011/0285023 A1 (Shen), in conjunction with US 2007/0181908 A1 (Otremba), US 2021/0143120 A1 (Heinrich) and US 2008/0224285 A1 (Lim), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein a thickness of the first and second NiP layers is in a range from 200 nm to 500 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein a thickness of the first and second NiP layers is in a range from 200 nm to 500 nm,’ is material to the inventive concept of the application at hand to provide a compact stacked structure with shortened current paths between a diode and a transistor.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2020/0321499 A1 (Satou) - A bonding structure is disclosed that bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.
US 2011/0024881 A1 (Bhagath) - A semiconductor device is disclosed including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack.
US 2007/0205253 A1 (Hubner) - A method is disclosed for connecting at least two metal layers by means of a diffusion soldering process, wherein each of the metal layers that is to be connected is plated with a respective solder layer prior to the diffusion soldering process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
06/25/2026
Prosecution Insights