DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/5/2024, 7/14/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 through 11 are objected to because of the following informalities:
Claim 1 recites “one ends” in line 9. The examiner suggests “first ends”.
Claim 9 recites “a a” in lines 3 and 4. The duplicate “a” is extraneous and should be deleted.
Appropriate correction is required.
Claims 2 through 20 depend from and incorporate claim 1
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first through vias" in line 10. There is insufficient antecedent basis for this limitation in the claim. The examiner suggests “the first through silicon vias”.
Claim 1 recites the limitation "the other ends" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claims 2 through 11 depend from and incorporate claim 1.
Claim 20 recites the limitation "the first chip" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 5, and 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Gandhi (US 2021/0366873)
Regarding claim 1.
Gandhi teaches:
A three-dimensional semiconductor package (fig 1:100; [para 0022]), comprising: a package substrate (fig 1,2:116; [para 0023]) having a first surface and a second surface opposite to the first surface;
a first redistribution layer (fig 2, annotated)on the first surface of the package substrate (fig 1,2:116; [para 0023]), the first redistribution layer (fig 2, annotated) having a first surface and a second surface opposite to each other, the second surface of the first redistribution layer (fig 2, annotated) facing the surface of the package substrate (fig 1,2:116; [para 0023]);
a first chip (fig 1,2:112; [para 0022]) on the first surface of the first redistribution layer, electrically connected (fig 2:130; [para 0030]) to the first redistribution layer, and comprising first through silicon vias (fig 1; [para 0032]);
first connection terminals (fig 1:124; [para 0032])electrically connected to one ends of the first through silicon vias (fig 1; [para 0032]), the other ends (fig 2:206; [para 0036]) of the first through vias ([para 0032]) being closer to the first redistribution layer (fig 2 annotated);
a second redistribution layer (fig 2 annotated) on the second surface of the package substrate (fig 1,2:116; [para 0023]), the second redistribution layer having a first surface and a second surface opposite to each other (fig 2 annotated), the first surface of the second redistribution layer facing the second surface of the package substrate (fig 1,2:116; [para 0023]);
and a second chip (fig 1:106; [para 0027]) on the second surface of the second redistribution layer (fig 2) and electrically connected (fig 1,2:154; [para 0036]) to the second redistribution layer, wherein the first redistribution layer and the second redistribution layer are interconnected (fig 2:210,212; [para 0036]) through the package substrate, and wherein the first chip (fig 1,2:112; [para 0022]) and the second chip (fig 1:106; [para 0027]) are disposed within a periphery of the package substrate (fig 1,2:116; [para 0023]) when viewed in a plan view.
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Regarding claim 2
Gandhi teaches the three-dimensional semiconductor package of claim 1,
wherein the first chip (fig 1,2:112; [para 0022]) comprises a logic chip ([para 0032]), and the second chip (fig 1:106; [para 0027]) comprises a cache chip ([para 0027]).
Regarding claim 3
Gandhi teaches the three-dimensional semiconductor package of claim 1,
wherein the package substrate (fig 1,2:116; [para 0023]) is not a silicon substrate or a silicon interposer (comprises dielectric ; [para 0036]).
Regarding claim 4
Gandhi teaches the three-dimensional semiconductor package of claim 1,
further comprising first connection members (fig 2:130; [para 0030]) between the first chip (fig 1,2:112; [para 0022]) and the first redistribution layer (fig 2 annotated) and electrically connecting the first chip (fig 1,2:112; [para 0022]) to the first redistribution layer (fig 2 annotated), and second connection members (fig 2:154; [para 0039]) between the second chip (fig 1:106; [para 0027]) and the second redistribution layer (fig 2 annotated) and electrically connecting the second chip (fig 1:106; [para 0027]) to the second redistribution layer, wherein the first connection members (fig 2:130; [para 0030]) and the second connection members (fig 2:154; [para 0039]) comprise micro-bumps (fig 2; [para 0030,0039]).
Regarding claim 5
Gandhi teaches the three-dimensional semiconductor package of claim 4,
further comprising a non-conductive film (fig 2:132; [para 0031]), wherein the non-conductive film (fig 2:132; [para 0031]) is disposed in a space between the first chip (fig 1,2:112; [para 0022]) and the first redistribution layer (fig 2 annotated) and around the first connection members (fig 2:130; [para 0030]).
Regarding claim 10
Gandhi teaches the three-dimensional semiconductor package of claim 1
Gandhi teaches:
a molding layer (fig 1:144; [para 0023]), at least a portion of the molding layer (fig 1:144; [para 0023]) disposed on the second surface of the package substrate (fig 1,2:116; [para 0023]) and on the second chip (fig 1:106; [para 0027]) and the second redistribution layer (fig 2 annotated).
Claim(s) 12, 13, 14, 15, and 16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Gandhi (US 2021/0366873)
Regarding claim 12.
Gandhi teaches:
A three-dimensional semiconductor package (fig 1:100; [para 0022]), comprising: a package substrate (fig 1,2:116; [para 0023]) having a first surface and a second surface opposite to the first surface (fig 2 annotated);
a first redistribution layer on the first surface of the package substrate (fig 1,2:116; [para 0023]);
a first chip (fig 1,2:112; [para 0022]) on the first redistribution layer and electrically connected (fig 2:130; [para 0030])to the first redistribution layer, and comprising first through silicon vias ([para 0032]);
first connection terminals (fig 1:124; [para 0032]) electrically connected to ends of the first through silicon vias ([para 0032]);
a second redistribution layer on the second surface of the package substrate (fig 1,2:116; [para 0023]);
and a second chip (fig 1:106; [para 0027]) on the second redistribution layer and electrically connected (fig 1,2:154; [para 0036]) to the second redistribution layer (fig 2 annotated), wherein the first chip (fig 1,2:112; [para 0022]) and the second chip (fig 1:106; [para 0027]) are disposed within a periphery of the package substrate (fig 1,2:116; [para 0023]) when viewed in a plan view.
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Regarding claim 13.
Gandhi teaches the three-dimensional semiconductor package of claim 12,
wherein the first chip (fig 1,2:112; [para 0022]) comprises a logic chip ([para 0032]), and the second chip (fig 1:106; [para 0027]) comprises a cache chip ([para 0027]).
Regarding claim 14.
Gandhi teaches the three-dimensional semiconductor package of claim 12,
Gandhi teaches:
first connection members (fig 2:130; [para 0030]) between the first chip (fig 1,2:112; [para 0022]) and the first redistribution layer (fig 2 annotated) and electrically connecting the first chip (fig 1,2:112; [para 0022]) to the first redistribution layer;
and second connection members (fig 2:154; [para 0039]) between the second chip (fig 1:106; [para 0027]) and the second redistribution layer (fig 2 annotated) and electrically connecting the second chip (fig 1:106; [para 0027]) to the second redistribution layer.
Regarding claim 15.
Gandhi teaches the three-dimensional semiconductor package of claim 14,
Gandhi teaches:
the first connection members (fig 2:130; [para 0030]) comprise micro-bumps ([para 0030]), and wherein the second connection members (fig 2:154; [para 0039]) comprise micro-bumps ([para 0039]).
Regarding claim 16.
Gandhi teaches the three-dimensional semiconductor package of claim 14,
Gandhi teaches:
a non-conductive film (fig 1:144; [para 0023]), wherein the non-conductive film (fig 1:144; [para 0023]) is disposed in a space between the first chip (fig 1,2:112; [para 0022]) and the first redistribution layer (fig 2 annotated) and around the first connection members (fig 2:130; [para 0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) as applied to claim 1 and further in view of Kim (US 2022/0189934).
Regarding claim 6.
Gandhi teaches the three-dimensional semiconductor package of claim 1,
Gandhi does not teach a plurality of first chips.
Kim teaches:
wherein the first chip is provided in plural so that there are a plurality of first chips (fig 6:442,602; [para 0042]), wherein the plurality of first chips (fig 6:442,602; [para 0042]) are disposed side by side on the first surface of the first redistribution layer (fig 6:513; [para 0040]), and wherein each of the plurality of first chips (fig 6:442,602; [para 0042]) is electrically connected to the first redistribution layer (fig 6:513; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first chips in order that chips having additional functions can be provide (paragraph 42)
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) as applied to claim 1 and further in view of Cheah (US 2019/0013301)
Regarding claim 7.
Gandhi teaches the three-dimensional semiconductor package of claim 1,
wherein the second chip (fig 1:106; [para 0027]) is provided in plural (fig 1) so that there are a plurality of second chips (fig 1:106; [para 0027]), wherein: the plurality of second chips (fig 1:106; [para 0027]) are sequentially stacked (fig 1:102; [para 0022]) on the second surface of the second redistribution layer (fig 2 annotated) and electrically connected (fig 1:108; [para 0028]) to each other , and a lowermost one of the plurality of second chips (fig 1:106; [para 0027]) is electrically connected to the second redistribution layer (fig 2 annotated).
Gandhi does not teach through silicon vias.
Cheah teaches:
the plurality of second chips (fig 1:102a-d; [para 0027]) are sequentially stacked on the second surface of the second redistribution layer (fig 1:106; [para 0028]) and electrically connected to each other through second through silicon vias (fig 1:105; [para 0029]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide through silicon vias in order to provide a shirt path connect the devices of each chip thereby limiting signal time.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) as applied to claim 1 and further in view of Yu (US 2015/0235989)
Regarding claim 8.
Gandhi teaches the three-dimensional semiconductor package of claim 1,
Gandhi does not teach second connection terminals has a size greater than that of each of the first connection terminals.
Yu teaches:
a plurality of second connection terminals (fig 1h,1L:26; [para 0028]) disposed on the first surface of the first redistribution layer (fig 1h,1l:18; [para 0028]), surrounding the first chip (fig 1h,1l:32; [para 0031]), and connected to the first redistribution layer (fig 1h,1l:32; [para 0031]), wherein each of the plurality of second connection terminals (fig 1h,1L:26; [para 0028]) has a size greater than that of each of the first connection terminals (fig 1h,1L:24; [para 0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first connection terminals to be smaller than the second connection terminals in order that the chip connections can be more closely spaced thereby enabling more connections and higher bandwidth.
Regarding claim 9.
Gandhi in view of Yu teaches the three-dimensional semiconductor package of claim 8,
Gandhi teaches:
wherein the plurality of second connection terminals (fig 1:118; [para 0036]) comprise at least one of a transmission terminal ([para 0036]) and a dummy terminal.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) as applied to claim 1 and further in view of Shih (US 2018/0102311).
Regarding claim 11.
Gandhi teaches the three-dimensional semiconductor package of claim 1,
Gandhi does not teach a plurality of second chips side by side.
Shih teaches:
the second chip is provided in plural so that there are a plurality of second chips (fig 14:11,12; [para 0051]), wherein: the plurality of second chips (fig 14:11,12; [para 0051])disposed side by side on the second surface of the second redistribution layer (fig 14:900; [para 0047]), and each of the plurality of second chips (fig 14:11,12; [para 0051]) is electrically connected to the second redistribution layer (fig 14:900; [para 0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multiple side by side chips in order to employ chips that do not use complex through silicon via structures thereby simplifying the manufacture.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) as applied to claim 12 and further in view of Kim (US 2022/0189934).
Regarding claim 17.
Gandhi teaches the three-dimensional semiconductor package of claim 12,
Gandhi does not teach a plurality of first chips.
Kim teaches:
the first chip is provided in plural so that there are a plurality of first chips (fig 6:442,602; [para 0042]), wherein the plurality of first chips (fig 6:442,602; [para 0042]) are disposed side by side on the first redistribution layer (fig 6:513; [para 0040]), and wherein each of the plurality of first chips (fig 6:442,602; [para 0042]) is electrically connected to the first redistribution layer (fig 6:513; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first chips in order that chips having additional functions can be provide (paragraph 42)
Claim(s) 18, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi (US 2021/0366873) in view of Kim (US 2022/0189934).
Regarding claim 18.
Gandhi teaches:
A three-dimensional semiconductor package (fig 1:100; [para 0022]), comprising: a package substrate (fig 1,2:116; [para 0023]) having a first surface and a second surface opposite to the first surface (fig 2 annotated);
a first redistribution layer on the first surface of the package substrate (fig 1,2:116; [para 0023]);
a first chips (fig 1,2:112; [para 0022]) on the first redistribution layer and electrically connected to the first redistribution layer (fig 2 annotated), and comprising first through silicon vias (fig 1; [para 0032]);
first connection terminals (fig 1:124; [para 0032])electrically connected to ends of the first through silicon vias (fig 1; [para 0032]);
a second redistribution layer on the second surface of the package substrate (fig 1,2:116; [para 0023]);
a plurality of second chips (fig 1:106; [para 0027]) on the second redistribution layer and electrically connected to the second redistribution layer (fig 2 annotated);
first connection members (fig 1:124; [para 0032]) between the first chips (fig 1,2:112; [para 0022]) and the first redistribution layer and electrically connecting the first chips (fig 1,2:112; [para 0022]) to the first redistribution layer;
and second connection members (fig 1,2:154; [para 0036]) between the plurality of second chips (fig 1:106; [para 0027]) and the second redistribution layer and electrically connecting the plurality of second chips (fig 1:106; [para 0027]) to the second redistribution layer (fig 2 annotated).
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Gandhi does not teach a plurality of first chips
Kim teaches:
wherein the first chip is provided in plural so that there are a plurality of first chips (fig 6:442,602; [para 0042]), wherein the plurality of first chips (fig 6:442,602; [para 0042]) are disposed on the first surface of the first redistribution layer (fig 6:513; [para 0040]), and wherein each of the plurality of first chips (fig 6:442,602; [para 0042]) is electrically connected to the first redistribution layer (fig 6:513; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of first chips in order that chips having additional functions can be provide (paragraph 42)
Regarding claim 19.
Gandhi in view of Kim teaches the three-dimensional semiconductor package of claim 18,
Gandhi teaches:
wherein the first chips (fig 1,2:112; [para 0022]) and the plurality of second chips (fig 1:106; [para 0027]) are disposed within a periphery of the package substrate (fig 1,2:116; [para 0023]) when viewed in a plan view (fig 1).
Regarding claim 20.
Gandhi in view of Kim teaches the three-dimensional semiconductor package of claim 18,
Gandhi teaches:
wherein the first chip (fig 1,2:112; [para 0022]) comprises a logic chip ([para 0032]), and the second chip (fig 1:106; [para 0027]) comprises a cache chip ([para 0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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