DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application is a CON of 17/408,230 08/20/2021 PAT 11935869 which is a CON of 16/942,619 07/29/2020 PAT 11114416 which is a CON of 16/169,915 10/24/2018 PAT 10748874.
Continued Examination under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114.
The request for continued examination has been entered on 02/10/2026.
In the request for continued examination, the applicants have been amended claims 1-3, 5, 9, 11, 13 and 18-19 and have been remained claims 4, 6-8, 10, 12, 14-17 and 20-25.
Claims 2-25 are currently pending in the application.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C 101 which states that “whoever invents or discovers any new and useful process…. May obtain a patent thereof …”
Thus, the term “same invention”, in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re vogel, 422 F2.d 438, 164 USPQ 619 (CCPA 1990); and In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created
doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the
unjustified or improper timewise extension of the "right to exclude" granted by a patent
and to prevent possible harassment by multiple assignees. See In re Goodman, 11
F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ
645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In
re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d
528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be
used to overcome an actual or provisional rejection based on a nonstatutory double
patenting ground provided the conflicting application or patent is shown to be commonly
owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
4. Claims 1-11 and 13-17 are rejected under the judicially created doctrine of obvious-type double patenting as being unpatentable over claims 1-11 and 13-17 of Brewer (U.S. Patent No. 11,935,869 B2), hereafter “’869 patent”. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the reasons set for the below.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Claims of the instant application
Claims of US Patent 11,935,869 B2
1. An apparatus comprising: a non-volatile memory die; a logic die; a volatile memory die; and an electrical temperature sensor configured to measure a temperature of a part of the logic die.
1. An apparatus comprising: a non-volatile memory die; a logic die; a volatile memory die, wherein the volatile memory die is arranged with the non-volatile memory die and the logic die; and an electrical temperature sensor configured to measure a temperature of a part of the logic die.
2. The apparatus of claim 1, wherein the volatile memory die is stacked with the non-volatile memory die and the logic die.
2. The apparatus of claim 1, wherein the volatile memory die is stacked with the non-volatile memory die and the logic die.
3. The apparatus of claim 1, wherein the volatile memory die is arranged with the non-volatile memory die and the logic die to form the array of functional blocks.
3. The apparatus of claim 1, wherein the volatile memory die is arranged with the non-volatile memory die and the logic die to form the array of functional blocks.
4. The apparatus of claim 1, further comprising: a thermal management component having a different thermal conductivity than the dies; wherein the thermal management component is stacked with the non-volatile memory die and the logic die.
4. The apparatus of claim 1, further comprising: a thermal management component having a different thermal conductivity than the dies; wherein the thermal management component is stacked with the non-volatile memory die and the logic die.
5. The apparatus of claim 1, wherein the temperature sensor is further configured to communicate the measured temperature to the volatile memory die, and the volatile memory die is further configured to store the measured temperature.
5. The apparatus of claim 1, wherein the temperature sensor is further configured to communicate the measured temperature to the volatile memory die, and the volatile memory die is further configured to store the measured temperature.
6. The apparatus of claim 1, wherein the electrical temperature sensor is a first electrical temperature sensor configured in an array of electrical temperature sensors, and each sensor of the array is coupled to a respective through silicon via (TSV) by a communicative coupling between the TSV and the respective sensor.
6. The apparatus of claim 1, wherein the electrical temperature sensor is a first electrical temperature sensor configured in an array of electrical temperature sensors, and each sensor of the array is coupled to a respective through silicon via (TSV) by a communicative coupling between the TSV and the respective sensor.
7. The apparatus of claim 1, wherein: the logic die comprises an array of logic partitions including a first logic partition; and the electrical temperature sensor is further configured to measure a first temperature of the first logic partition, and communicate the first temperature to a memory partition of the non-volatile memory die.
7. The apparatus of claim 1, wherein: the logic die comprises an array of logic partitions including a first logic partition; and the electrical temperature sensor is further configured to measure a first temperature of the first logic partition, and communicate the first temperature to a memory partition of the non-volatile memory die.
8. The apparatus of claim 1, further comprising: a heat exchange medium between the non-volatile memory die and the logic die; wherein the electrical temperature sensor is further configured to measure a first temperature of the heat exchange medium, and communicate the first temperature to the non-volatile memory die.
8. The apparatus of claim 1, further comprising: a heat exchange medium between the non-volatile memory die and the logic die; wherein the electrical temperature sensor is further configured to measure a first temperature of the heat exchange medium, and communicate the first temperature to the non-volatile memory die.
9. The apparatus of claim 1, wherein the measured temperature is a first temperature, the apparatus further comprising: a port configured to communicatively couple the volatile memory die to a controller; wherein the electrical temperature sensor is further configured to measure a second temperature, and communicate the second temperature to the volatile memory die; wherein the volatile memory die is configured to: store the second temperature; receive, via the port, a request of a controller for the second temperature; and in response to receiving the request, communicate, via the port, the second temperature to the controller.
9. The apparatus of claim 1, wherein the measured temperature is a first temperature, the apparatus further comprising: a port configured to communicatively couple the volatile memory die to a controller; wherein the electrical temperature sensor is further configured to measure a second temperature, and communicate the second temperature to the volatile memory die; wherein the volatile memory die is configured to: store the second temperature; receive, via the port, a request of a controller for the second temperature; and in response to receiving the request, communicate, via the port, the second temperature to the controller.
10. The apparatus of claim 9, wherein the controller is configured to: in response to receiving the second temperature, identify whether the second temperature exceeds a predetermined threshold; and in response to identifying that the second temperature exceeds the predetermined threshold, reduce usage of at least one of the functional blocks.
10. The apparatus of claim 9, wherein the controller is configured to: in response to receiving the second temperature, identify whether the second temperature exceeds a predetermined threshold; and in response to identifying that the second temperature exceeds the predetermined threshold, reduce usage of at least one of the functional blocks.
11. (Currently Amended) An apparatus comprising: a non-volatile memory die; a volatile memory die; an electrical temperature sensor; and a logic die.
13. (Currently Amended) The apparatus of claim 11, wherein the electrical temperature sensor is configured to measure a temperature, and communicate the measured temperature to one of the memory dies.
11. An apparatus comprising: a non-volatile memory die; a volatile memory die; a thermal management component having a different thermal conductivity than the dies; and a logic die.
13. The apparatus of claim 11, further comprising an electrical temperature sensor configured to measure a temperature, and communicate the measured temperature to one of the non-volatile memory die and volatile memory die.
14. (Original) The apparatus of claim 13, further comprising a heat exchange medium between the non-volatile memory die and the logic die, wherein the measured temperature is a temperature of the heat exchange medium.
14. The apparatus of claim 13, further comprising a heat exchange medium between the non-volatile memory die and the logic die, wherein the measured temperature is a temperature of the heat exchange medium.
15. (Original) The apparatus of claim 13, further comprising a controller configured to: request the measured temperature; in response to receiving the measured temperature, identify whether the measured temperature exceeds a predetermined threshold; and in response to identifying that the measured temperature exceeds the predetermined threshold, reduce usage of at least one of the functional blocks.
15. The apparatus of claim 13, further comprising a controller configured to: request the measured temperature; in response to receiving the measured temperature, identify whether the measured temperature exceeds a predetermined threshold; and in response to identifying that the measured temperature exceeds the predetermined threshold, reduce usage of at least one of the functional blocks.
16. (Original) The apparatus of claim 13, wherein the logic die is configured to: identify whether the measured temperature exceeds a threshold; and in response to identifying that the measured temperature exceeds the threshold, reduce usage of at least a first functional block.
16. The apparatus of claim 13, wherein the logic die is configured to: identify whether the measured temperature exceeds a threshold; and in response to identifying that the measured temperature exceeds the threshold, reduce usage of at least a first functional block.
17. (Original) The apparatus of claim 16, wherein the logic die is further configured to: in response to identifying that the measured temperature does not exceed the threshold, change usage of the first functional block from reduced usage to normal usage.
17. The apparatus of claim 16, wherein the logic die is further configured to: in response to identifying that the measured temperature does not exceed the threshold, change usage of the first functional block from reduced usage to normal usage.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over MOON et al., hereafter “MOON” (U.S. Publication No. 2014/0181439 A1) in view of HSIAO et al., hereafter “HSIAO” (U.S. Publication No. 2015/0021755 A1).
Regarding claim 11, MOON discloses an apparatus comprising:
a non-volatile memory die (NVMD, para [0025]);
a volatile memory die (VMD1/VMD2/VMD3/VMD4); and
a logic die (200, para [0049]) (Fig. 7).
MOON discloses the features of the claimed invention as discussed above, but does not disclose an electrical temperature sensor.
HSIAO, however, discloses temperature sensors (55A) and (55B) are resistive temperature sensors that indicate a change in temperature by a change in electrical resistance (Fig. 3 and para [0047]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of MOON to provide an electrical temperature sensor as taught by HSIAO for a purpose of increasing the accuracy of measurements and quick stabilization of temperature in the apparatus.
Allowable Subject Matter
6. The following is a statement of reason for the indication of allowable subject matter:
Claims 18-25 would be allowed.
Claims 18-25 are considered allowable since the prior art of record and the considered pertinent to the applicant’s disclosure does not teach or suggest the claimed invention of an apparatus having wherein the non-volatile memory die, the volatile memory die, and the logic die are stacked to form an array of functional blocks, as cited in the independent claim 18.
Claims 19-25 are directly or indirectly depend on the independent claim 18, then, they are also being allowed.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art of records disclose further comprising: a thermal management component having a different thermal conductivity than the dies; wherein the thermal management component is stacked with the non-volatile memory die, the volatile memory die, and the logic die, as cited in claim 12.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897