DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of claims 1, 6-20 without traverse in the reply filed on 08/24/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 10, 12, 14, 16-20 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by KANAKAMEDALA et al. (US 20200251443 A1)
Regarding claim 1, KANAKAMEDALA teaches,
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A semiconductor structure for hybrid bonding, the semiconductor structure comprising:
a first structure(70W or 90W comprising 700 or 900 , Fig. 2A, 6C) comprising a bonding surface (bonding surface of 700 or 900 in FIG. 6C) and a surface opposite of the bonding surface,
wherein the bonding surface comprises conductive areas (144, para [0073]) and dielectric areas (960, para [0074]); and
a film (1017, para [0062], Fig. 2A on the backside of wafer 70W or 90W) overlaying the first structure on the surface of the first structure that is opposite of the bonding surface,
wherein the film comprises one or more stressed portions that compensate for warpage in the first structure (see para [0062]-[0063], “An area in which warpage of the first wafer (70W or 90W) is below a predefined threshold may be assigned as the first area, and an area in which warpage of the first wafer (70W or 90W) is above the predefined threshold may be assigned as the second area” , “ multiple etch mask layers 1017 may be employed to pattern the stress-generating film 1010 into multiple areas (2-8 areas)
Regarding claim 6, KANAKAMEDALA teaches,
A method of forming a semiconductor structure, the method comprising:
forming a first structure (70W comprising 700 , Fig. 2A, 6C) comprising a bonding surface (bonding surface with 900, FIG. 6C) and a surface opposite the bonding surface,
wherein the bonding surface comprises conductive areas (144/788, para [0073]) and dielectric areas(960/760, para [0074]);
and forming a film (1017 patterned by stress generating film 1010, para [0062], Fig. 2A on the backside of wafer 70W or 90W) overlaying the first structure on the surface of the first structure that is opposite of the bonding surface,
wherein the film comprises one or more stressed portions that compensate for warpage in the first structure(see para [0062]-[0063], “An area in which warpage of the first wafer (70W or 90W) is below a predefined threshold may be assigned as the first area, and an area in which warpage of the first wafer (70W or 90W) is above the predefined threshold may be assigned as the second area” , “ multiple etch mask layers 1017 may be employed to pattern the stress-generating film 1010 into multiple areas (2-8 areas).
Regarding claim 10, KANAKAMEDALA teaches the method of claim 6 and further teaches further comprising removing the film from the first structure (stress generating film 1010 is removed (para [0064], the etch mask layer 1017 is removed, para [0062])
Regarding claim 12, KANAKAMEDALA teaches the method of claim 6 and further teaches , further comprising: contacting the first structure with a second structure (900, FIG. 6C) formed in a die (wafer 90W, FIG. 2A) , the second structure comprising a second bonding surface (boding surface with 700, FIG. 6C) , and the second bonding surface comprising second conductive areas (788) and second dielectric areas (760); and bonding the first structure to the second structure, wherein the bonding surface of the first structure is hybrid bonded to the bonding surface of the second structure, such that the conductive areas (144) of the first structure (700) contacts the second conductive areas (788) of the second structure(900) (as seen in FIG. 6C) .
Regarding claim 14, KANAKAMEDALA teaches,
A method comprising: obtaining data for a semiconductor structure (70W or 90W in FIG. 2A) that is indicative of warpage locations (see para [0062], “An area in which warpage of the first wafer (70W or 90W) is below a predefined threshold may be assigned as the first area, and an area in which warpage of the first wafer (70W or 90W) is above the predefined threshold may be assigned as the second area. Various algorithms may be employed to shift the boundary between the first area and the second area. The algorithm may divide the area of the first wafer (70W or 90W) into multiple zones (such as 2-24 zones) having different levels, or types, of vertical deformation (deviation from a horizontal plane), and various algorithms may be employed to generate a map of the first area from which the etch mask layer 1017 is to be removed and the second area in which the etch mask layer 1017 is to remain”);
and causing stress to be induced into one or more portions of a film (pattern the stress generating film 1010 using etch mask pattern , para [0063]) on the semiconductor structure to create one or more stressed portions that compensate for the warpage locations (see para [0062] “the warpage of the first wafer (70W or 90W) can be measured after depositing the stress-generating film 1010 on the backside of the first wafer (70W or 90W)” and “various algorithms may be employed to generate a map of the first area from which the etch mask layer 1017 is to be removed and the second area in which the etch mask layer 1017 is to remain)
Regarding claim 16, KANAKAMEDALA teaches the method of claim 14 and further teaches , further comprising determining one or more sizes and one or more shapes for the one or more stressed portions (para [0062]-[0063], “multiple etch mask layers 1017 may be employed to pattern the stress-generating film 1010 into multiple areas (2-8 areas )” )
Regarding claim 17, KANAKAMEDALA teaches the method of claim 14 and further teach further comprising determining a material for the film ( material used for film 1010) .
Regarding claim 18, KANAKAMEDALA teaches the method of claim 14 does not explicitly teach ,further comprising determining a film thickness for the film ( thickness used for the film 1010) .
Regarding claim 19, KANAKAMEDALA teaches the method of claim 14 and further teaches , wherein the film thickness is between about 1 nm and about 10 nm.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the thickness in a range between about 1 nm and about 10 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 20, KANAKAMEDALA teaches the method of claim 14 and further teaches ,wherein the film material comprises a dielectric material ( etch mask layer 1017 can be photo resist layer, para [0061] , a photoresist is generally dielectric as widely known in art).
Allowable Subject Matter
Claims 7-8-9, 11, 13 & 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 7, 8, 11, 3 & 15 the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
further comprising: forming a photoresist layer over the film;
determining areas for each of one or more recesses to place in the stressed portions of the film; applying photolithography to the photoresist layer based on the areas for each of the one or more recesses to form a second set of one or more recesses in the photoresist layer,
wherein the second set of one or more recesses corresponds to the one or more recesses; and
applying an etchant to the photoresist layer and the film to form the one or more recesses in the film(claim 7)
further comprising: applying a first amount of heat to a first portion of the film to form a first stress zone in the first structure; and applying a second amount of heat to a second portion of the film, wherein the first amount of heat is different from the second amount of heat to form a second stress zone in the first structure, and the first portion and the second portion correspond to a first location and second location, respectively, of warpage in the first structure(claim 8).
further comprising: contacting the first structure with a second structure formed in a wafer, the second structure comprising a second bonding surface, and the second bonding surface comprising second conductive areas and second dielectric areas; and bonding the first structure to the second structure, wherein the bonding surface of the first structure is hybrid bonded to the bonding surface of the second structure, such that the conductive areas of the first structure contacts the second conductive areas of the second structure(claim 11).
further comprising removing the film from the first structure after bonding the first structure to the second structure(claim 13)
further comprising determining first locations of warpage in the semiconductor structure by performing a metrology test on the semiconductor structure; and determining second locations to induce stress into one or more stressed portions of a dielectric film overlaying the semiconductor structure to create one or more stress zones in the semiconductor structure, wherein the one or more stress zones correspond to the first locations of warpage(claim 15)
Claim 9 objected to being dependent on claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
