DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 March 2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6, 8 – 13, and 15 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rao et al. US Patent Application Publication No. 2015/0206277 (herein after referred to as Rao).
Regarding claim 1, Rao describes one or more processors (…unified memory support is provided across multiple heterogeneous processors. With unified memory support in a system, data can be accessed using the same pointer from the CPU and the GPU in that system. However, for systems that contain multiple GPUs, the same pointer has to be accessible across all GPUs that are capable of supporting unified memory (page 9, paragraph [0107])), comprising: circuitry to (With reference to Fig. 9, a block diagram of an exemplary computer system 900… (page 3, paragraph [0054]). Computing Systems are known to be comprised of circuits), in response to an application programming interface (API) call (…through an application program interface (API) (e.g., like cudaMalloc, etc.) (page 2, paragraph [0032])), allocate virtual memory and cause graphics processing unit (GPU) storage or host storage to be mapped to the allocated virtual memory (In block 1310, a memory allocation process is performed. In one embodiment, a memory allocation process similar to an address allocation process in block 120 is performed. In one exemplary implementation, a CudaMalloc call is made, memory is allocated on a GPU and a CPU, and a CPU PA space is mapped to a GPU VA space (page 5, paragraph [0068])).
Regarding claim 2, Rao describes the one or more processors of claim 1 (see above), wherein the circuitry is to allocate the virtual memory based, at least in part, on a flag in memory of one or more second processors (When a user passes in a special flag called managed memory it indicates it is one unified memory (page 6, paragraph [0080]). …a “host” flag may be used instead for the argument which means that the data will only be touched from the CPU side, so anything the GPU may be doing to the data will not affect it… (page 13, paragraph [0157]). While the call “CudaMallocManaged” will allocate on the GPU, the flag (global, host, etc.) indicates who will be accessing the data (page 13, paragraph [0159])).
Regarding claim 3, Rao describes the one or more processors of claim 1 (see above), wherein the circuitry is to allocate the virtual memory based, at least in part, on a descriptor to create the virtual memory (…a “host” flag may be used instead for the argument which means that the data will only be touched from the CPU side, so anything the GPU may be doing to the data will not affect it… (page 13, paragraph [0157])).
Regarding claim 4, Rao describes the one or more processors of claim 1 (see above), wherein the allocated virtual memory comprises a range of memory (In one embodiment, the allocator maintains an internal heap of the VA address ranges it has reserved on the CPU (e.g., using mmap in block 210, etc.). This heap represents the GPU allocations. Now given a VA pointer, the allocator or the runtime can determine if this is a GPU allocation or a CPU allocation by looking up the heap (page 3, paragraph [0043]). These are essentially windows or ranges into the GPU memory (page 6, paragraph [0077]). The device driver can create the mapping by using a window or range and shifting and creating a CPU to VA mapping, then the device driver can read and write the memory itself and then send the content back to the user debugger (page 6, paragraph [0078])).
Regarding claim 5, Rao describes the one or more processors of claim 1 (see above), wherein the host storage is storage of a central processing unit (CPU) (Many computing systems often have a central processing unit (CPU)… (page 1, paragraph [0007]). …unified memory architectures or schemes (e.g., compatible with CUDA 6.0, etc.) can result in cases where the same memory can be accessed on a host (e.g., CPU, etc.)… (page 5, paragraph [0063]). In one embodiment, a host is a CPU and a device is a GPU (page 6, paragraph [0075])).
Regarding claim 6, Rao describes the one or more processors of claim 1 (see above), wherein one or more GPUs are to reserve the virtual memory based, at least in part, on the API call (The GPU driver reserves one or more regions from the CPU’s virtual address space. The same or similar set of regions are also reserved in the GPUs virtual address space (page 7, paragraph [0084]). If CUDAmalloc managed is used a chunk of CPU VA or reserved region is picked and the physical pages or actual physical memory on the GPU is allocated and then in the GPU VA space set up mapping from GPU page table (e.g., from that region set up mapping to that physical memory, etc.) (page 8, paragraph [0100])).
Regarding claim 8, Rao describes a system, comprising: one or more processors (…unified memory support is provided across multiple heterogeneous processors. With unified memory support in a system, data can be accessed using the same pointer from the CPU and the GPU in that system. However, for systems that contain multiple GPUs, the same pointer has to be accessible across all GPUs that are capable of supporting unified memory (page 9, paragraph [0107])) to, in response to an application programming interface (API) call (…through an application program interface (API) (e.g., like cudaMalloc, etc.) (page 2, paragraph [0032])), allocate virtual memory and cause graphics processing unit (GPU) storage or host storage to be mapped to the allocated virtual memory (In block 1310, a memory allocation process is performed. In one embodiment, a memory allocation process similar to an address allocation process in block 120 is performed. In one exemplary implementation, a CudaMalloc call is made, memory is allocated on a GPU and a CPU, and a CPU PA space is mapped to a GPU VA space (page 5, paragraph [0068])).
Regarding claim 9, Rao describes the system of claim 8 (see above), wherein the one or more processors are to allocate the virtual memory based, at least in part, on information including a location in memory of one or more second processors (The presented new approach or solution uses OS allocation on the CPU combined with GPU driver mappings to provide a unified VA across both GPU and CPU (page 2, paragraph [0030]). Virtual addresses associated with the GPU can be mapped to the GPU PA. In one embodiment, GPU VA 410 allocated space 411 (including an address associated with pointer 412) is mapped to GPU PA 430 address 431 via GPU PTE 420 mapping entry or indication 421… Virtual addresses associated with the CPU can be mapped to the CPU PA. The CPU VA 440 address associated with pointer 433 is mapped to CPU PA 450 address 451 via CPU PTE 470 mapping entry or indication 471… (page 3, paragraph [0048])).
Regarding claim 10, Rao describes the system of claim 8 (see above), wherein the one or more processors are to allocate the virtual memory based, at least in part, on a descriptor to reserve the virtual memory (The GPU driver reserves one or more regions from the CPU’s virtual address space. The same or similar set of regions are also reserved in the GPUs virtual address space (page 7, paragraph [0084]). If CUDAmalloc managed is used a chunk of CPU VA or reserved region is picked and the physical pages or actual physical memory on the GPU is allocated and then in the GPU VA space set up mapping from GPU page table (e.g., from that region set up mapping to that physical memory, etc.) (page 8, paragraph [0100]). …a “host” flag may be used instead for the argument which means that the data will only be touched from the CPU side, so anything the GPU may be doing to the data will not affect it… (page 13, paragraph [0157])).
Regarding claim 11, Rao describes the system of claim 8 (see above), wherein the one or more processors access a range of memory of the GPU storage or the host storage (In one embodiment, the allocator maintains an internal heap of the VA address ranges it has reserved on the CPU (e.g., using mmap in block 210, etc.). This heap represents the GPU allocations. Now given a VA pointer, the allocator or the runtime can determine if this is a GPU allocation or a CPU allocation by looking up the heap (page 3, paragraph [0043]). These are essentially windows or ranges into the GPU memory (page 6, paragraph [0077]). The device driver can create the mapping by using a window or range and shifting and creating a CPU to VA mapping, then the device driver can read and write the memory itself and then send the content back to the user debugger (page 6, paragraph [0078])).
Regarding claim 12, Rao describes the system of claim 8 (see above), wherein the host storage is storage of a central processing unit (CPU) (Many computing systems often have a central processing unit (CPU)… (page 1, paragraph [0007]). …unified memory architectures or schemes (e.g., compatible with CUDA 6.0, etc.) can result in cases where the same memory can be accessed on a host (e.g., CPU, etc.)… (page 5, paragraph [0063]). In one embodiment, a host is a CPU and a device is a GPU (page 6, paragraph [0075])).
Regarding claim 13, Rao describes the system of claim 8 (see above), wherein one or more GPUs are to reserve the virtual memory based, at least in part, on the API call (The GPU driver reserves one or more regions from the CPU’s virtual address space. The same or similar set of regions are also reserved in the GPUs virtual address space (page 7, paragraph [0084]). If CUDAmalloc managed is used a chunk of CPU VA or reserved region is picked and the physical pages or actual physical memory on the GPU is allocated and then in the GPU VA space set up mapping from GPU page table (e.g., from that region set up mapping to that physical memory, etc.) (page 8, paragraph [0100])).
Regarding claim 15, Rao describes a method, comprising: receiving an application programming interface (API) call (…through an application program interface (API) (e.g., like cudaMalloc, etc.) (page 2, paragraph [0032])) comprising a parameter indicating a location of physical memory to be used for virtual memory to be allocated ; and in response to the API call, allocating the virtual memory and causing the virtual memory to be mapped to the location of the physical memory, wherein the physical memory is located in graphics processing unit (GPU) storage or host storage (In block 1310, a memory allocation process is performed. In one embodiment, a memory allocation process similar to an address allocation process in block 120 is performed. In one exemplary implementation, a CudaMalloc call is made, memory is allocated on a GPU and a CPU, and a CPU PA space is mapped to a GPU VA space (page 5, paragraph [0068])).
Regarding claim 16, Rao describes the method of claim 15 (see above), wherein the parameter is a flag in memory to indicate the host storage when a default is device storage (When a user passes in a special flag called managed memory it indicates it is one unified memory (page 6, paragraph [0080]). …a “host” flag may be used instead for the argument which means that the data will only be touched from the CPU side, so anything the GPU may be doing to the data will not affect it… (page 13, paragraph [0157]). While the call “CudaMallocManaged” will allocate on the GPU, the flag (global, host, etc.) indicates who will be accessing the data (page 13, paragraph [0159])).
Regarding claim 17, Rao describes the method of claim 15 (see above), further comprising generating a flag to indicate a host memory allocation when creating one or more blocks of memory (When a user passes in a special flag called managed memory it indicates it is one unified memory (page 6, paragraph [0080]). …a “host” flag may be used instead for the argument which means that the data will only be touched from the CPU side, so anything the GPU may be doing to the data will not affect it… (page 13, paragraph [0157]). While the call “CudaMallocManaged” will allocate on the GPU, the flag (global, host, etc.) indicates who will be accessing the data (page 13, paragraph [0159])).
Regarding claim 18, Rao describes the method of claim 15 (see above), further comprising indicating a range of memory of the GPU storage or the host storage (In one embodiment, the allocator maintains an internal heap of the VA address ranges it has reserved on the CPU (e.g., using mmap in block 210, etc.). This heap represents the GPU allocations. Now given a VA pointer, the allocator or the runtime can determine if this is a GPU allocation or a CPU allocation by looking up the heap (page 3, paragraph [0043]). These are essentially windows or ranges into the GPU memory (page 6, paragraph [0077]). The device driver can create the mapping by using a window or range and shifting and creating a CPU to VA mapping, then the device driver can read and write the memory itself and then send the content back to the user debugger (page 6, paragraph [0078])).
Regarding claim 19, Rao describes the method of claim 15 (see above), wherein the host storage is storage of a central processing unit (CPU) (Many computing systems often have a central processing unit (CPU)… (page 1, paragraph [0007]). …unified memory architectures or schemes (e.g., compatible with CUDA 6.0, etc.) can result in cases where the same memory can be accessed on a host (e.g., CPU, etc.)… (page 5, paragraph [0063]). In one embodiment, a host is a CPU and a device is a GPU (page 6, paragraph [0075])).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rao in view of Trout et al. US Patent Application Publication No. 2020/0073809 (herein after referred to as Trout).
Regarding claim 7, Rao describes the one or more processors of claim 1 (see above). While Rao discloses that the invention provides for improved parallel processing performance of parallel processing-capable applications using unified memory because the total amount of page migration is reduced (page 10, paragraph [0121]). However, Rao does not specifically describe wherein the circuitry is to cause access to the GPU storage or the host storage using a route optimizing bandwidth between the one or more processors.
Trout describes handling of a memory system during a processor side cache miss. Specifically, it discloses that the memory sub-system may provide an application programming interface (API) that includes an allocation function (page 3, paragraph [0040]). Furthermore, an API may provide tools to facilitate supporting advanced memory addressing techniques, such as different memory access patterns abstracted under the concept of an access axis. For example, an access axis may provide sufficient information (e.g., metadata) to enable a memory sub-system to access stored data in straight (e.g., address) order, a striding order, and/or a sorted order. In any case, at least in some instances, implementing and operating a computing system in this manner may facilitate improving operational (e.g., power and/or communication) efficiency, for example, by reducing data retrieval latency, reducing data communication via a system bus, and/or increasing communication bandwidth available to other computing subsystems (page 7, paragraph [0068]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Trout teachings in the Rao system. Skilled artisan would have been motivated to incorporate the method of enabling access of stored data in various orders as taught by Trout in the Rao system for effectively improving operational efficiency, by increasing communication bandwidth available to other computing sub-systems (Trout, page 7, paragraph [0068]). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as memory allocation facilitated by API. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 14, Rao describes the system of claim 8 (see above). While Rao discloses that the invention provides for improved parallel processing performance of parallel processing-capable applications using unified memory because the total amount of page migration is reduced (page 10, paragraph [0121]). However, Rao does not specifically describe wherein the one or more processors are to cause access of storage using a route optimizing bandwidth between the one or more processors.
Trout describes handling of a memory system during a processor side cache miss. Specifically, it discloses that the memory sub-system may provide an application programming interface (API) that includes an allocation function (page 3, paragraph [0040]). Furthermore, an API may provide tools to facilitate supporting advanced memory addressing techniques, such as different memory access patterns abstracted under the concept of an access axis. For example, an access axis may provide sufficient information (e.g., metadata) to enable a memory sub-system to access stored data in straight (e.g., address) order, a striding order, and/or a sorted order. In any case, at least in some instances, implementing and operating a computing system in this manner may facilitate improving operational (e.g., power and/or communication) efficiency, for example, by reducing data retrieval latency, reducing data communication via a system bus, and/or increasing communication bandwidth available to other computing subsystems (page 7, paragraph [0068]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Trout teachings in the Rao system. Skilled artisan would have been motivated to incorporate the method of enabling access of stored data in various orders as taught by Trout in the Rao system for effectively improving operational efficiency, by increasing communication bandwidth available to other computing sub-systems (Trout, page 7, paragraph [0068]). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as memory allocation facilitated by API. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 20, Rao describes the method of claim 15 (see above). While Rao discloses that the invention provides for improved parallel processing performance of parallel processing-capable applications using unified memory because the total amount of page migration is reduced (page 10, paragraph [0121]). However, Rao does not specifically describe further comprising causing access of storage using a route optimizing bandwidth between one or more processors.
Trout describes handling of a memory system during a processor side cache miss. Specifically, it discloses that the memory sub-system may provide an application programming interface (API) that includes an allocation function (page 3, paragraph [0040]). Furthermore, an API may provide tools to facilitate supporting advanced memory addressing techniques, such as different memory access patterns abstracted under the concept of an access axis. For example, an access axis may provide sufficient information (e.g., metadata) to enable a memory sub-system to access stored data in straight (e.g., address) order, a striding order, and/or a sorted order. In any case, at least in some instances, implementing and operating a computing system in this manner may facilitate improving operational (e.g., power and/or communication) efficiency, for example, by reducing data retrieval latency, reducing data communication via a system bus, and/or increasing communication bandwidth available to other computing subsystems (page 7, paragraph [0068]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Trout teachings in the Rao system. Skilled artisan would have been motivated to incorporate the method of enabling access of stored data in various orders as taught by Trout in the Rao system for effectively improving operational efficiency, by increasing communication bandwidth available to other computing sub-systems (Trout, page 7, paragraph [0068]). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as memory allocation facilitated by API. This close relation between both of the references highly suggests an expectation of success.
Response to Arguments
Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner notes that the amendments to the independent claims broadened the scope of previously objected to claims 7, 14, and 20. These claims have been reconsidered in view of the broadened scope.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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May 12, 2026
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