DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/5/2024 and 3/21/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. US 2020/0013754 in view of Hagimoto et al. US 2013/0207271.
Re claim 1, Gao teaches a semiconductor package (fig1), comprising:
a lower structure (102’, fig1, [34]); and
an upper structure (102 directly above 102’, fig1, [34]) disposed on the lower structure (102’, fig1, [34]),
wherein the lower structure (102’, fig1, [34]) comprises: a first substrate (104, fig1, [34]);
a first through-electrode (114, fig1, [39]) that penetrates the first substrate in a first direction (from top surface to bottom surface, fig1);
a first pad (110 of 102’, fig1, [37]) connected to the first through-electrode (114, fig1, [39]); and
a first protective layer (106 of 102’, fig1, [39]) that surrounds the first pad (110 of 102’, fig1, [37]),
wherein the upper structure (102 directly above 102’, fig1, [34]) comprises: a second substrate (104 of lower 102, fig1, [35]);
a second through-electrode (114 of lower 102, fig1, [39]) that penetrates the second substrate in the first direction;
a second pad (110 of lower 102, fig1, [37]) connected to the second through-electrode; and
a second protective layer (106 of lower 102, fig1, [39]) that surrounds the second pad,
wherein the second pad (110 of lower 102, fig1, [37]) is offset from the first pad (110 of 102’, fig1, [37]) in a second direction (left to right, fig1) that crosses the first direction (from top surface to bottom surface, fig1),
wherein the first pad (110 of 102’, fig1, [37]) includes a first portion (part of 110 of 102’ not in contact with 110 in lower 102, fig1) that does not overlap the second pad (110 of lower 102, fig1, [37]),
Gao does not explicitly show wherein the semiconductor package further comprises: a first barrier pattern disposed between the first portion and the second protective layer, wherein a portion of the first barrier pattern is disposed between the first pad and the second pad.
Hagimoto teaches a first barrier pattern (35B, fig4, [62]) disposed between the first portion (part of 33B not covered by 33A, fig4, [61]) and the second protective layer (32A, fig4, [61]), wherein a portion of the first barrier pattern (35B in contact with 35A, fig4, [62]) is disposed between the first pad (33B, fig4, [61]) and the second pad (33A, fig4, [61]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao and Hagimoto to add a barrier layer 35A/B between the direct bond pads. The motivation to do so is to improve the reliability of the bonding device by preventing void generating in the bonding interface (Hagimoto, [61]).
Re claim 2, Gao modified above teaches the semiconductor package of claim 1, wherein the second pad (Hagimoto, 33A, fig4, [61]) includes a second portion (Hagimoto, part of 33A not covered by 33B, fig4, [61]) that does not overlap the first pad (Hagimoto, 33B, fig4, [61]), wherein the semiconductor package further comprises: a second barrier pattern (Hagimoto, 35A, fig4, [62]) disposed between the second portion (Hagimoto, part of 33A not covered by 33B, fig4, [61]) and the first protective layer (Hagimoto, part of 32B, fig4, [61]), wherein a portion of the second barrier pattern (Hagimoto, part of 35A covered by 33B, fig4, [61]) is disposed between the first pad (Hagimoto, 33B, fig4, [61]) and the second pad (Hagimoto, 33A, fig4, [61]).
Re claim 3, Gao modified above teaches the semiconductor package of claim 2, wherein the first and second barrier patterns (Hagimoto, 35A/B, fig4, [62]) are connected to each other and are disposed along an edge of the first pad (Hagimoto, 33B, fig4, [61]), when viewed in a plan view.
Re claim 4, Gao modified above teaches the semiconductor package of claim 1, wherein the first barrier pattern (Hagimoto, 35B, fig4, [62]) includes at least one of Ti (Hagimoto, [62]), Ta (Hagimoto, [62]), or TiN.
Re claim 6, Gao modified above teaches the semiconductor package of claim 1, wherein a thickness of the first barrier pattern in the first direction ranges from 1Å to 100Å (Hagimoto, 35, fig4, [69]).
Re claim 7, Gao modified above teaches the semiconductor package of claim 1, wherein the first barrier pattern (Hagimoto, 35B, fig4, [62]) is disposed between the first protective layer (Hagimoto, 32B, fig4, [61]) and the second protective layer (Hagimoto, 32A, fig4, [61]).
Claim(s) 10, 11, 13, 15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. US 2020/0013754 in view of Hagimoto et al. US 2013/0207271 and Lii et al. US 2022/0238353.
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Re claim 10, Gao teaches a semiconductor package (fig1), comprising:
a lower structure (102’, fig1, [34]); and
an upper structure (102 directly above 102’, fig1, [34]) disposed on the lower structure,
wherein the lower structure (102’, fig1, [34]) comprises: a first pad (110 of 102’, fig1, [37]); and
a first protective layer (106 of 102’, fig1, [39]) that surrounds a side surface of the first pad,
wherein the upper structure (102 directly above 102’, fig1, [34]) comprises: a second pad (110 of lower 102, fig1, [37]); and
a second protective layer (106 of lower 102, fig1, [39]) that surrounds a side surface of the second pad,
wherein a top surface of the first pad (110 of 102’, fig1, [37]) is partially in contact with a bottom surface of the second pad (110 of lower 102, fig1, [37]),
wherein the first pad (110 of 102’, fig1, [37]) includes: a first offset portion (part of 110 in 102’not covered by 110 in 102, fig1, [37]) adjacent to the second protective layer (106 of lower 102, fig1, [39]); and
a first overlapping portion (part of 110 in 102’ covered by 110 in 102, fig1, [37]) that overlaps the second pad (110 of lower 102, fig1, [37]),
wherein the second pad (110 of lower 102, fig1, [37]) includes: a second offset portion (110 of lower 102 not covered by 110 in 102’, fig1, [37]) adjacent to the first protective layer (106 of 102’, fig1, [39]); and
a second overlapping portion (110 of lower 102 covered by 110 in 102’, fig1, [37]) that overlaps the first pad,
Gao does not explicitly show wherein a first barrier pattern is disposed between the first offset portion and the second protective layer and between the first overlapping portion and the second pad, and wherein a second barrier pattern is disposed between the second offset portion and the first protective layer and between the second overlapping portion and the first pad.
Hagimoto teaches a first barrier pattern (35B, fig4, [62]) is disposed between the first offset portion (part of 33B not covered by 33A, fig4, [61]) and the second protective layer (32A, fig4, [61]) and between the first overlapping portion (part of 33B covered by 33A, fig4, [61]) and the second pad (33A, fig4, [61]), and wherein a second barrier pattern (35A, fig4, [62]) is disposed between the second offset portion (part of 33A not covered by 33B, fig4, [61]) and the first protective layer (32B, fig4, [61]) and between the second overlapping portion (part of 33A covered by 33B, fig4, [61]) and the first pad (33B, fig4, [61]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao and Hagimoto to add a barrier layer 35A/B between the direct bond pads. The motivation to do so is to improve the reliability of the bonding device by preventing void generating in the bonding interface (Hagimoto, [61]).
Lii teaches forming a first barrier pattern (58A of Ti, Ta or TiN as a diffusion barrier, fig18A, [33]) between first pad (54’ and lower part of 59 formed by 58B, fig18A, [33, 37, 41]) and a second barrier pattern (158A of Ti, Ta or TiN as a diffusion barrier, fig18A, [33]) between second pad (154’ and upper part of 59 formed by 158B, fig18A, [33, 37, 41]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao in view of Hagimoto and Lii replace 35A with 158A/B and replace 35B with 58A/B and use the Ti, Ta, TiN layer 158A/58A as the first and second barrier pattern with center part containing 158B/58B forming 59 as part of first/second pad. The motivation to do so is to prevent diffusion of metal to the dielectric layer and prevent gap generating in the bonding interface (Lii, [11, 41]).
Re claim 11, Gao modified above teaches the semiconductor package of claim 10, wherein each of the first barrier pattern (Hagimoto, Ti, Ta or TiN added between 35B and 33B, fig4, [61, 62]) and the second barrier pattern (Hagimoto, Ti, Ta or TiN added between 35A and 33A, fig4, [61, 62]) includes at least one of Ti (Lii, 58A/158A as Ti, fig17, [33]), Ta (Lii, 58A/158A as Ta, fig17, [33]), or TiN (Lii, 58A/158A as TiN, fig17, [33]).
Re claim 13, Gao modified above teaches the semiconductor package of claim 10, wherein a thickness of each of the first barrier pattern and the second barrier pattern ranges from 1Å to 100Å (Hagimoto, 35, fig4, [69]).
Re claim 15, Gao modified above teaches the semiconductor package of claim 10, wherein the first and second barrier patterns (Hagimoto, Ti, Ta or TiN added between 35B and 33B and between 35A and 33A, fig4, [61, 62]) are connected to each other and are disposed along an edge of the first pad (Lii, fig18A), when viewed in a plan view.
Re claim 17, Gao teaches a semiconductor package (200, fig1 and 3, [43]), comprising:
a lower structure (102’, fig1, [34]); and
an upper structure (102 directly above 102’, fig1, [34]) disposed on the lower structure,
wherein the lower structure (102’, fig1, [34]) comprises: a first substrate (104, fig1, [34]) that includes a first device region (DRAM in 104 of 102’, fig1, [75]);
a first through-electrode (114, fig1, [39]) that penetrates the first substrate in a first direction (from top surface to bottom surface, fig1);
a first pad (110 of 102’, fig1, [37]) connected to the first through-electrode; and
a first protective layer (106 of 102’, fig1, [39]) that surrounds the first pad,
wherein the upper structure (102 directly above 102’, fig1, [34]) comprises: a second substrate (104 of lower 102, fig1, [35]) that includes the first device region (DRAM in 104 of 102’, fig1, [75]);
a second through-electrode (114 in 102, fig1, [39]) that penetrates the second substrate in the first direction;
a second pad (110 of lower 102, fig1, [37]) connected to the second through-electrode; and
a second protective layer (106 of lower 102, fig1, [39]) that surrounds the second pad,
wherein the second pad (110 of lower 102, fig1, [37]) is offset from the first pad (110 of 102’, fig1, [37]) in a second direction (left to right, fig1) that crosses the first direction and is in contact with the first pad,
Gao does not explicitly show wherein the semiconductor package further comprises a first barrier pattern disposed between the first pad and the second pad, wherein the first barrier pattern includes: a first barrier portion disposed on an edge of a top surface of the first pad; a second barrier portion disposed on an edge of a bottom surface of the second pad, wherein the first barrier portion and the second barrier portion partially overlap each other, a first single portion disposed between the first pad and the second protective layer; and an overlap portion disposed between the first pad and the second pad and where the first barrier portion overlaps the second barrier portion, and wherein a thickness of the first single portion is less than a thickness of the overlap portion.
Hagimoto teaches a first barrier pattern (35B, fig4, [62]) disposed between the first pad (33B, fig4, [61]) and the second pad (33A, fig4, [61]), wherein the first barrier pattern (35B, fig4, [62]) includes: a first barrier portion (35B not in contact with 35A, fig4, [62]) disposed on an edge of a top surface of the first pad (33B, fig4, [61]); a second barrier portion (35A, fig4, [62]) disposed on an edge of a bottom surface of the second pad (33A, fig4, [61]), wherein the first barrier portion (35B, fig4, [62]) and the second barrier portion (35A, fig4, [62]) partially overlap each other, a first single portion (part of 35B in contact with 36A, fig4, [62]) disposed between the first pad (33B, fig4, [61]) and the second protective layer (32A, fig4, [61]); and an overlap portion (center part of 35B and 35A, fig4, [62]) disposed between the first pad and the second pad and where the first barrier portion overlaps the second barrier portion, and wherein a thickness of the first single portion is less than a thickness of the overlap portion (fig4).
Lii teaches forming a first barrier pattern (58A of Ti, Ta or TiN as a diffusion barrier, fig18A, [33]) between first pad (54’ and lower part of 59 formed by 58B, fig18A, [33, 37, 41]) and a second barrier pattern (158A of Ti, Ta or TiN as a diffusion barrier, fig18A, [33]) between second pad (154’ and upper part of 59 formed by 158B, fig18A, [33, 37, 41]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao in view of Hagimoto and Lii replace 35A with 158A/B and replace 35B with 58A/B and use the Ti, Ta, TiN layer 158A/58A as the first and second barrier pattern with center part containing 158B/58B forming 59 as part of first/second pad. The motivation to do so is to prevent diffusion of metal to the dielectric layer and prevent gap generating in the bonding interface (Lii, [11, 41]).
Re claim 18, Gao modified above teaches the semiconductor package of claim 17, wherein the first barrier pattern (Hagimoto, Ti, Ta or TiN added between 35B and 33B, fig4, [61, 62]) further includes: a second single portion (Hagimoto, part of Ti, Ta or TiN added under 35A facing 36B, fig4, [62]) that is a portion of the second barrier portion (Hagimoto, Ti, Ta or TiN added between 35A and 33A, fig4, [61, 62]) that does not overlap the first barrier portion (Hagimoto, Ti, Ta or TiN added between 35B and 33B not facing 35A, fig4), wherein the second single portion (Hagimoto, part of Ti, Ta or TiN added under 35A facing 36B, fig4, [62]) is disposed between the first pad and the second pad (see figure above), and wherein a thickness of the second single portion is less than the thickness of the overlap portion (see figure above).
Re claim 19, Gao modified above teaches the semiconductor package of claim 17, wherein the first barrier pattern includes at least one of Ti, Ta, or TiN (Hagimoto, Ti, Ta or TiN added between 35B and 33B, fig4, [61, 62]).
Re claim 20, Gao modified above teaches the semiconductor package of claim 17, wherein a width in the second direction of the first barrier portion differs from a width in the second direction of the second barrier portion (Gao, with upper 110 smaller than 110 in 202, fig3).
Claim(s) 5, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. US 2020/0013754 in view of Hagimoto et al. US 2013/0207271 and Hou et al. US 2021/0327838.
Re claim 5, Gao does not explicitly show the semiconductor package of claim 1, wherein a length of the first barrier pattern in the second direction ranges from 0.1μm to 8μm.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with width of 100nm-300nm. The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Re claim 8, Gao does not explicitly show the semiconductor package of claim 1, wherein a planar shape of the first pad is one of a circular shape, a tetragonal shape, a hexagonal shape, or a polygonal shape.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]) with a horizontal cross-section of a rectangle or circular shape ([88]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with a horizontal cross-section of a rectangle or circular shape with width of 100nm-300nm . The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Re claim 9, Gao does not explicitly show the semiconductor package of claim 1, wherein a planar shape of the first barrier pattern is one of a circular shape, a cogwheel shape, a triangular shape, a tetragonal shape, or a polygonal shape.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]) with a horizontal cross-section of a rectangle or circular shape ([88]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with a horizontal cross-section of a rectangle or circular shape with width of 100nm-300nm . The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Claim(s) 12, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. US 2020/0013754 in view of Hagimoto et al. US 2013/0207271, Lii et al. US 2022/0238353 and Hou et al. US 2021/0327838.
Re claim 12, Gao does not explicitly show the semiconductor package of claim 10, wherein a width of each of the first barrier pattern and the second barrier pattern ranges from 0.1μm to 8μm.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with width of 100nm-300nm. The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Re claim 14, Gao does not explicitly show the semiconductor package of claim 10, wherein a planar shape of each of the first pad and the second pad is one of a circular shape, a tetragonal shape, a hexagonal shape, or a polygonal shape.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]) with a horizontal cross-section of a rectangle or circular shape ([88]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with a horizontal cross-section of a rectangle or circular shape with width of 100nm-300nm . The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Re claim 16, Gao does not explicitly show the semiconductor package of claim 10, wherein a planar shape of each of the first barrier pattern and the second barrier pattern is one of a circular shape, a cogwheel shape, a triangular shape, a tetragonal shape, or a polygonal shape.
Hou teaches bonding pads with width of 100nm-300nm (488, fig19A, [147]) with a horizontal cross-section of a rectangle or circular shape ([88]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Gao modified above and Hou to add a barrier layer between the direct bond pads with a horizontal cross-section of a rectangle or circular shape with width of 100nm-300nm . The motivation to do so is to improve memory array density and form easier interconnection (Hou, [49]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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