Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1, reading on claims 1-4, 6-10 in the reply filed on 08/24/2026 is acknowledged.
Claims 5, 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/24/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 9, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (US 20150262987 A1; hereinafter “Wada”).
In re claim 1, Wada discloses, in figs. 13A-13B, a semiconductor device comprising:
a wiring board 1 (¶85) including first (e.g., top surface; hereinafter “S1”) and second surfaces (e.g., bottom surface; hereinafter “S2”) opposite to each other;
a first semiconductor element 3 (¶84-86; in fig. 13, LED element 3 is underneath the top translucent fluorescent plate 4) on the first surface side of the wiring board S1;
a second semiconductor element 5 (¶84-85) adjacent to the first semiconductor element 3 on the first surface side of the wiring board;
a first resin composition 7L on the first surface side of the wiring board S1 (¶133-136); and
a second resin composition 7H that covers the first and second semiconductor elements 3, 5 and the first resin composition 7L (¶133-136),
wherein the first resin composition 7L includes:
a first part (e.g., a first part of 7L underneath LED chip 3; hereinafter “Part1”) between the first surface of the wiring board S1 and a surface (e.g., a bottom surface) of the first semiconductor element 3 facing the first surface S1, and
a second part (e.g., a second part of 7L contacting left side surface of the second chip 5; hereinafter “Part2”) contacting a first side surface (e.g., a left side surface) of the second semiconductor element 5 facing the first semiconductor element 3.
In re claim 2, Wada discloses, in figs. 13A-13B, the semiconductor device according to claim 1, wherein the first semiconductor element 3 is a flip chip (¶86).
In re claim 4, Wada discloses, in figs. 13A-13B, the semiconductor device according to claim 1, wherein the first resin composition 7L contacts a side surface of the first semiconductor element 3 facing the first side surface of the second semiconductor element 5.
In re claim 6, Wada discloses, in figs. 13A-13B, the semiconductor device according to claim 1, further comprising: a third semiconductor element (another LED chip 3 as shown in the plan view of figs. 1-6) (¶84-86) adjacent to the first semiconductor element 3 on the first surface side of the wiring board S1, wherein the first resin composition 7L includes a third part (e.g., a part between adjacent LEDs 3) contacting a side surface of the third semiconductor element 3 facing the first semiconductor element 3.
In re claim 9, Wada discloses, in figs. 13A-13B, the semiconductor device according to claim 1, further comprising:
an intermediate layer 2 between the first surface of the wiring board S1 and the first semiconductor element 3 (¶84, 86),
wherein the first resin composition 7L contacts a side surface of the intermediate layer 2 facing the first semiconductor element 3.
In re claim 10, Wada discloses, in figs. 13A-13B, the semiconductor device according to claim 1,
wherein the first resin composition 7L includes
a third part (e.g., a third part of 7L contacting right side surface of the first chip 3; hereinafter “Part3”) contacting a side surface (e.g., right side surface) of the first semiconductor element 3 facing the first side surface of the second semiconductor element 5 and
a fourth part (e.g., a middle part of 7L between the first chip 3 and the second chip 5; hereinafter “Part4”) between the second and third parts of the first resin composition (Part2, Part3), and
a height of the fourth part (Part4) is lower than a height of each of the second and third parts (Part2, Part3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa et al. (US 20150069632 A1; hereinafter “Ozawa”) in view of Chang et al. (US 20230082912 A1; hereinafter “Chang”).
In re claim 1, Ozawa discloses, in fig. 12, a semiconductor device comprising:
a wiring board 11 (¶36) including first (e.g., top surface; hereinafter “S1”) and second surfaces (e.g., bottom surface; hereinafter “S2”) opposite to each other;
a first semiconductor element 12 (¶28) on the first surface side of the wiring board S1;
a second semiconductor element 25 (¶46) adjacent to the first semiconductor element 12 on the first surface side of the wiring board S1;
a first resin composition 28 (¶31, 36, 46; “The mold members 16 and 17 may be a resin containing the same material or resins containing different materials”; mold member 28 is same as mold member 16) on the first surface side of the wiring board S1; and
a second resin composition 17 (¶35-36) that covers the first and second semiconductor elements 12, 25 and the first resin composition 28,
wherein the first resin composition 28 includes:
a second part (e.g., a part between chip 12 and chip 25) contacting a first side surface of the second semiconductor element 25 facing the first semiconductor element 12.
Ozawa does not expressly disclose the first resin composition includes a first part between the first surface of the wiring board and a surface of the first semiconductor element facing the first surface.
In the same field of endeavor, Chang discloses, in fig. 5, a semiconductor device wherein first resin composition 161c includes:
a first part between an upper surface of a wiring board 111c and a surface of a first semiconductor element 120c facing the upper surface (¶52).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chang into the package Ozawa to further enhance mechanical reliability of the devices inside the semiconductor package.
In re claim 3, Ozawa as modified by Chang discloses the semiconductor device according to claim 1 outlined above.
Ozawa further discloses, in fig. 12, wherein the second semiconductor element 25 and the wiring board 11 are connected by a bonding wire 27 (¶46).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Chang, as applied to claim 1 above, and further in view of Ohhashi et al. (US 20220020658 A1; hereinafter “Ohhashi”).
In re claim 7, Ozawa as modified by Chang discloses the semiconductor device according to claim 1 outlined above.
Ozawa as modified by Chang does not expressly disclose wherein the first and second semiconductor elements are arranged along a first direction,
a width of the first semiconductor element in the first direction is substantially identical to a length thereof in a second direction perpendicular to the first direction,
a width of the second semiconductor element in the first direction is smaller than the width of the first semiconductor element and a length of the second semiconductor element in the second direction, and
the length of the second semiconductor element is greater than the length of the first semiconductor element.
In the same field of endeavor, Ohhashi discloses, in figs. 15, a semiconductor device according to claim 1,
wherein a first and a second circuit areas 402, 403 on a sub-mount substrate 101g are arranged along a first direction Y (¶223),
wherein first area 402 corresponds to an output matching circuit of driver amplifier 501, and second area 403 corresponds to the power distribution circuit and/or the input matching circuit.
Ohhashi further depicts a width of the first circuit area in the first direction X (e.g., W1) is substantially identical to a length (e.g., L1) thereof in a second direction Y perpendicular to the first direction (fig. 15 shows first area 402 as substantially a square shaped area),
a width of the second circuit area 402 in the first direction X (e.g., W2) is smaller than the width of the first circuit area 402 and a length of the second circuit area (e.g., L2) in the second direction Y, and
the length of the second circuit area L2 is greater than the length of the first circuit area L1.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Ohhashi into the package Ozawa as modified by Chang such that different circuitry with different power requirements can be accommodated in a semiconductor package.
Furthermore, it has been held to be within the general skill of a worker in the art to select relative sizes and shapes of the various semiconductor elements in a package on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select relative sizes and shapes of the various semiconductor elements in a package in order to meet the power requirements of individual devices in the package.
In re claim 8, Ozawa as modified by Chang and Ohhashi discloses semiconductor device according to claim 7 outlined above.
Ozawa as modified by Chang and Ohhashi does not expressly disclose wherein a ratio of the length of the second semiconductor element to the width thereof is between 1 and 10.
However, it has been held to be within the general skill of a worker in the art to select relative sizes and shapes of the various semiconductor elements in a package on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select relative sizes and shapes of the various semiconductor elements in a package in order to meet the power requirements of individual devices in the package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheon et al. (US 20160240396 A1; hereinafter “Cheon”) discloses, in fig. 9, a semiconductor device 200 comprising:
a wiring board 10 (¶55) including first (e.g., top surface; hereinafter “S1”) and second surfaces (e.g., bottom surface; hereinafter “S2”) opposite to each other;
a first semiconductor element 12 (see fig. 9 annotated below; hereinafter “Dev1”) on the first surface side of the wiring board S1;
a second semiconductor element 12 (see fig. 9 annotated below; hereinafter “Dev2”) adjacent to the first semiconductor element 12 on the first surface side of the wiring board S1;
a first resin composition 238 (¶70) on the first surface side of the wiring board S1; and
a second member 210 that covers the first and second semiconductor elements (Dev1, Dev2) and the first resin composition 238 (¶54),
wherein the first resin 238 composition includes:
a first part between the first surface of the wiring board S1 and a surface of the first semiconductor element (Dev1) facing the first surface S1, and
a second part contacting a first side surface of the second semiconductor element (Dev2) facing the first semiconductor element (Dev1).
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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