Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/25/24, 04/13/26 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims #1-17 and 23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/18/26.
Claims #18-22 will be further examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim #19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
With respect to Claim #19, which currently states, “wherein the array region is substantially free of the additional insulative structures”, the Examiner notes that the current specifications and drawings designate the ‘array region’ (as seen in fig. 1G, as item 160), as item #160. However, the current specifications and drawings show and define the ‘insulative structures’ as being directly underneath the defined area for ‘substantially free’ area. The Examiner cannot differentiate, in light of the present specifications or drawings, what area or amount of area/region, is substantially free of claimed additional insulative structures. The Examiner takes the position that one of ordinary skill in the art, at the time of original conception, could not reproduce said described invention without undue experimentation.
Furthermore, with respect to claim #19, the term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from ‘substantially free’. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is substantially free), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Correction to these matters is requested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. Pat. No, 9,960,180), hereinafter referred to as "Zhou" and in view of Ikawa et al., (U.S. Pat. No. 9,589,839), hereinafter referred to as "Ikawa".
Zhou shows, with respect to claim #18, a memory device, comprising: a stack structure (column #1, line 26-42) comprising: an array region comprising a vertically alternating sequence of insulative structures (fig. #2, item 32) and conductive structures (fig. #2, item 42; silicon nitride) arranged in tiers (column #6, line 28-46; column #7, line 30-35; column #15, line 58-62); and a peripheral region comprising a vertically alternating sequence of the insulative structures (fig. #2, item 32) and additional insulative structures (fig. #5, item 12) arranged in additional tiers horizontally neighboring the tiers of the array region (column #10, line 3-8), at least some of the additional insulative structures (fig. #16, item 54, 56) (column #11, line 43-67).
Zhou substantially shows the claimed invention as shown in the rejection of claim #18 above.
Zhou fails to show, with respect to claim #18, a device comprising silicon nitride comprising greater than or equal to about 1.60 silicon atoms for every about 1.00 nitrogen atom. and strings of memory cells in the array region of the stack structure and comprising a channel material vertically extending through the stack structure.
Ikawa teaches, with respect to claim #18, a device comprising silicon nitride comprising greater than or equal to about 1.60 silicon atoms for every about 1.00 nitrogen atom. and strings of memory cells in the array region of the stack structure and comprising a channel material vertically extending through the stack structure (column #8, line 18-35).
The term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as " almost or nearly used to indicate that a number, amount, time, etc., is not exact or certain” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from about 1.60 silicon atoms for every about 1.00 nitrogen atom in order to be considered “about” 1.60 silicon atoms for every “about” 1.00 nitrogen atom. The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is about 1.60 silicon atoms for every about 1.00 nitrogen atom) and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #18, to modified the invention of Zhou as modified by the invention of Ikawa, which teaches, a device comprising silicon nitride comprising greater than or equal to about 1.60 silicon atoms for every about 1.00 nitrogen atom. and strings of memory cells in the array region of the stack structure and comprising a channel material vertically extending through the stack structure, to incorporate a structural wherein the silicon rich presence reduces the charge accumulation, as taught by Ikawa.
Zhou shows, with respect to claim #19, a device wherein the array region (fig. #8, item 73; contact region fig. #8, item 300) is substantially free of the additional insulative structures (column #10, lines 25-31; column #15, lines 18-40).
Zhou shows, with respect to claim #20, a device wherein each of the additional insulative structures (fig. #4, items 32 and 42) horizontally neighbors and is positioned at substantially the same vertical elevation as one of conductive structures (fig. #4a, item 32 and 42) (column #7, lines 1-7; column #9, lines 42-48).
Zhou shows, with respect to claim #21, a device wherein the strings of memory cells further comprise a memory material comprising silicon nitride (fig. #4a, item 32 and 42) (column #11, lines 63-67; column #12, lines 1-7).
Zhou fails to show, with respect to claim #22, a device a device wherein a ratio of nitrogen atoms to silicon atoms of the at least some of the additional insulative structures is greater than about 1.62:1.00.
Ikawa teaches, with respect to claim #22, a device a device wherein a ratio of nitrogen atoms to silicon atoms of the at least some of the additional insulative structures is greater than about 1.62:1.00 (column #8, line 18-35).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #22, to modified the invention of Zhou as modified by the invention of Ikawa, which teaches, a device wherein a ratio of nitrogen atoms to silicon atoms of the at least some of the additional insulative structures is greater than about 1.62:1.00, to incorporate a structural wherein the silicon rich presence reduces the charge accumulation, as taught by Ikawa.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims #18-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1 of Lengade et al., (U.S. Patent No. U.S. 12,004,346), hereinafter referred to as "Lengade". Although the claims at issue are not identical, they are not patentably distinct from each other because;
Claim #18 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 12,004,346, which discloses, microelectronic device, comprising: a stack structure including an array region and a peripheral region horizontally neighboring the array region, the stack structure comprising: a first region comprising first levels respectively comprising: silicon oxide material within the array region and the peripheral region; within the array region, conductive material vertically adjacent the silicon oxide material; and within the peripheral region, silicon nitride material vertically adjacent the silicon oxide material and having a first refractive index and a first ratio of nitrogen atoms to silicon atoms greater than about 1.60:1.00; and a second region vertically overlying the first region and including second levels respectively comprising: the silicon oxide material within the array region and the peripheral region; within the array region, the conductive material vertically adjacent the silicon oxide material; and within the peripheral region, additional silicon nitride material vertically adjacent the silicon oxide material, the additional silicon nitride material having a second refractive index greater than the first refractive index and having a second ratio of nitrogen atoms to silicon atoms less than about 1.60:1.00; and a third region vertically overlying the second region and including third levels respectively comprising: the silicon oxide material within the array region and the peripheral region; within the array region, the conductive material vertically adjacent the silicon oxide material; and within the peripheral region, the silicon nitride material vertically adjacent the silicon oxide material; and strings of memory cells vertically extending through the stack structure and horizontally confined within the array region of the stack structure. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 12,004,346, produces the same semiconductor structure as that in claim #18 of the instant application, which states, a memory device, comprising: a stack structure comprising: an array region comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers; and a peripheral region comprising a vertically alternating sequence of the insulative structures and additional insulative structures arranged in additional tiers horizontally neighboring the tiers of the array region, at least some of the additional insulative structures comprise silicon nitride comprising greater than or equal to about 1.60 silicon atoms for every about 1.00 nitrogen atom. and strings of memory cells in the array region of the stack structure and comprising a channel material vertically extending through the stack structure.
Claim #22 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 12,004,346, which discloses, microelectronic device, comprising: a stack structure including an array region and a peripheral region horizontally neighboring the array region, the stack structure comprising: a first region comprising first levels respectively comprising: silicon oxide material within the array region and the peripheral region; within the array region, conductive material vertically adjacent the silicon oxide material; and within the peripheral region, silicon nitride material vertically adjacent the silicon oxide material and having a first refractive index and a first ratio of nitrogen atoms to silicon atoms greater than about 1.60:1.00; and a second region vertically overlying the first region and including second levels respectively comprising: the silicon oxide material within the array region and the peripheral region; within the array region, the conductive material vertically adjacent the silicon oxide material; and within the peripheral region, additional silicon nitride material vertically adjacent the silicon oxide material, the additional silicon nitride material having a second refractive index greater than the first refractive index and having a second ratio of nitrogen atoms to silicon atoms less than about 1.60:1.00; and a third region vertically overlying the second region and including third levels respectively comprising: the silicon oxide material within the array region and the peripheral region; within the array region, the conductive material vertically adjacent the silicon oxide material; and within the peripheral region, the silicon nitride material vertically adjacent the silicon oxide material; and strings of memory cells vertically extending through the stack structure and horizontally confined within the array region of the stack structure. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 12,004,346, produces the same semiconductor structure as that in claim #22 of the instant application, which states, a memory device wherein a ratio of nitrogen atoms to silicon atoms of the at least some of the additional insulative structures is greater than about 1.62:1.00.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Pertinent art
Pertinent art, not relied on in the present rejection, but considered to be related to the claimed filed invention, will be listed below.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights