DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-4 in the reply filed on 7/1/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/6/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka US 2019/0296148 in view of Nunotani et al. US 2021/0066130.
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Re claim 1, Tanaka teaches a semiconductor device (fig1-4) comprising:
a conductive layer (22, fig3, [34]);
a semiconductor portion (10, fig3, [34]) provided on the conductive layer (22, fig3, [34]);
a first source electrode (20a, fig3, [34]) provided on the semiconductor portion (10, fig3, [34]);
a second source electrode (20b, fig3, [34]) provided on the semiconductor portion (10, fig3, [34]) and provided away from the first source electrode (20a, fig3, [34]);
a first control electrode (26a with gate insulating film 28a around, fig3, [34]) that is provided on the semiconductor portion (10, fig3, [34]) and that is electrically isolated from the first source electrode (20a, fig3, [34]) and the second source electrode (20b, fig3, [34]); and
a second control electrode (26b with gate insulating film 28b around, fig3, [34]) that is provided on the semiconductor portion (10, fig3, [34]) and that is electrically isolated from the first source electrode (20a, fig3, [34]), the second source electrode (20b, fig3, [34]), and the first control electrode (26a, fig3, [34]), the semiconductor portion (10, fig3, [34]) including a first semiconductor region (30, 32, fig3, [34]) of a first conductivity type (n-type, fig3, [50]) provided on the conductive layer (22, fig3, [34]),
a second semiconductor region (34a, fig3, [34]) of a second conductivity type (p-type, fig3, [51]) provided on the first semiconductor region, a third semiconductor region (34b, fig3, [34]) of the second conductivity type (p-type, fig3, [51]) provided on the first semiconductor region (30, 32, fig3, [34]) and provided away from the second semiconductor region (34a, fig3, [34]), a fourth semiconductor region (36a, fig3, [34]) of the first conductivity type (n-type, fig3, [51]) provided on the second semiconductor region (34a, fig3, [34]), and a fifth semiconductor region (36b, fig3, [34]) of the first conductivity type (n-type, fig3, [51]) provided on the third semiconductor region (34b, fig3, [34]), the first source electrode (20a, fig3, [34]) being electrically connected to the second semiconductor region (34a, fig3, [34]) and the fourth semiconductor region (36a, fig3, [34]), the second source electrode (20b, fig3, [34]) being electrically connected to the third semiconductor region (34b, fig3, [34]) and the fifth semiconductor region (36b, fig3, [34]), the first control electrode (26a, fig3, [34]) facing the first semiconductor region (30, 32, fig3, [34]), the second semiconductor region (34a, fig3, [34]), and the fourth semiconductor region (36a, fig3, [34]) via a first insulating film (28a, fig3, [34]), the second control electrode (26b, fig3, [34]) facing the first semiconductor region (30, 32, fig3, [34]), the third semiconductor region (34b, fig3, [34]), and the fifth semiconductor region (36b, fig3, [34]) via a second insulating film (28b, fig3, [34]), and in a plan view (fig1).
Tanaka does not explicitly show a first end portion of the conductive layer being located inside a second end portion of the semiconductor portion, and an outer periphery formed by the first end portion surrounding both at least a part of a third end portion of a first element region including the second semiconductor region and at least a part of a fourth end portion of a second element region including the third semiconductor region.
Nunotani teaches a first end portion of the conductive layer (region of 20 around CG, fig8A, [47]) being located inside a second end portion of the semiconductor portion (region of 17 around CG and side of 13, fig8A, [47]),
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tanaka and Nunotani to form a groove CG in the dicing region. The motivation to do so is to prevent chipping and cracking during the dicing process (Nunotani, [52]) and prevent solder from creeping upward during bonding process (Nunotani, [45]).
Tanaka in view of Nunotani teaches an outer periphery (Tanaka, region of 30 and 22 formed with CG, fig3) formed by the first end portion (Tanaka, region 22 formed with CG, fig8A, [47]) surrounding both at least a part of a third end portion (Tanaka, part of p type 34a in contact with 38, fig3) of a first element region including the second semiconductor region (Tanaka, 34a, fig3, [34]) and at least a part of a fourth end portion (Tanaka, part of p type 34b in contact with 38, fig3) of a second element region including the third semiconductor region (Tanaka, 34b, fig3, [34]).
Re claim 2, Tanaka in view of Nunotani teaches the device according to claim 1, wherein the first end portion (Tanaka, side of 22 with CG, fig3) is located outside the third end portion (Tanaka, part of p type 34a in contact with 38, fig3) and outside the fourth end portion (Tanaka, part of p type 34b in contact with 38, fig3) in a plan view.
Re claim 3, Tanaka in view of Nunotani teaches the device according to claim 1, wherein the third end portion (Tanaka, part of p type 34a in contact with 38, fig3) coincides with an end portion of the second semiconductor region (Tanaka, end of 34a in contact with 38, fig3, [34]) and the fourth end portion (Tanaka, part of p type 34b in contact with 38, fig3) coincides with an end portion of the third semiconductor region (Tanaka, end of 34b in contact with 38, fig3, [34])in a plan view.
Re claim 4, Tanaka in view of Nunotani teaches the device according to claim 1, wherein the conductive layer (Tanaka, 22, fig3, [34]) is a frustum having an upper surface (Tanaka, top surface of 22 facing 10, fig3, [34]) facing the semiconductor portion (Tanaka, 10, fig3, [34]) and a lower surface (Tanaka, bottom surface of 22 facing away from 10, fig3, [34]) located on a side opposite to the upper surface, and the frustum becomes thinner from the upper surface toward the lower surface (see figure above).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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