Attorney’s Docket Number: P202302968US01
Filing Date: 03/06/2024
Claimed Foreign Priority Date: none
Applicants: Xie et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application filed on 03/06/2024.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/596,803 filed on 03/06/2024 has been entered. Pending in this Office Action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 10, 12-14, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al. (US2024/0355879).
Regarding Claim 1, Song (see, e.g., Figs. 1 and 2A-C) shows all aspects of the instant invention including a semiconductor device comprising:
- a plurality of first transistors (e.g., lower transistor structures 106)
- a plurality of second transistors (e.g., upper transistor structures 108) stacked on the plurality of first transistors
- a plurality of gate isolation regions (e.g., gate isolation including contact insulators 248 in gate contact openings 250) disposed through respective gate structures of the plurality of second transistors (e.g., through gate electrodes 112 of 108)
- a plurality of gate contacts (e.g., gate contacts 122) disposed through the plurality of gate isolation regions, wherein the plurality of gate contacts contact respective gate structures of the plurality of first transistors
- wherein respective ones of the plurality of gate isolation regions are located at respective cell boundaries of the plurality of second transistors (see, e.g., Fig. 2C: gate isolation including 248 at cell boundaries of adjacent transistors 108).
Regarding Claim 3, Song (see, e.g., Fig. 2C) shows that the respective cell boundaries of the plurality of second transistors (e.g., 108) are offset with respect to respective cell boundaries of the plurality of first transistors (e.g., 106).
Regarding Claim 10, Song (see, e.g., Fig. 2C) shows that the plurality of first transistors (e.g., 106) and the plurality of second transistors (e.g., 108) comprise a plurality of nanosheet transistors respectively including a plurality of stacked channel regions (e.g., gate-all-around (GAA) transistors including stacked channel regions 118 and 120 respectively).
Regarding Claim 12, Song (see, e.g., Fig. 2C) shows that the plurality of gate isolation regions respectively comprise at least one dielectric layer (e.g., 248) disposed between a gate contact (e.g., 122) of the plurality of gate contacts and a gate structure (e.g., 112) of a second transistor of the plurality of second transistors.
Regarding Claim 13, Song (see, e.g., Fig. 2C) shows a plurality of additional gate isolation regions (e.g., insulating layer regions 226) disposed through respective gate structures (e.g., gate electrodes 110) of the plurality of first transistors (e.g., 106), wherein the plurality of additional gate isolation regions are offset from the plurality of gate isolation regions.
Regarding Claim 14, Song (see, e.g., Figs. 1 and 2A-C) shows all aspects of the instant invention including a semiconductor device comprising:
- a first transistor structure (e.g., lower transistor structure 106)
- a second transistor structure (e.g., upper transistor structure 108) stacked on the first transistor structure
- a gate contact (e.g., gate contact 122) disposed through a gate structure of the second transistor structure (e.g., through gate electrode 112), wherein the gate contact contacts a gate structure of the first transistor structure (e.g., gate electrode 110), and is isolated from the gate structure of the second transistor structure by a dielectric layer disposed on sides of the gate contact (e.g., contact insulator 248)
- wherein the dielectric layer is located at a cell boundary of the second transistor structure (see, e.g., Fig. 2C: 248 at cell boundary of 108).
Regarding Claim 18, Song (see, e.g., Figs. 1 and 2A-C) shows all aspects of the instant invention including a semiconductor device comprising:
- a first device layer (e.g., lower layer comprising lower transistor structures 106)
- a second device layer stacked on the first device layer (e.g., upper layer comprising upper transistor structures 108)
- a plurality of gate isolation regions (e.g., gate isolations including contact insulators 248 in gate contact openings 250) disposed through respective gate structures of the second device layer (e.g., through gate electrodes 112 of 108), wherein the plurality of gate isolation regions overlap respective areas between adjacent transistors in the first device layer (see, e.g., Fig. 2C)
- a plurality of gate contacts (e.g., gate contacts 122) disposed through the plurality of gate isolation regions, wherein the plurality of gate contacts contact gate structures in the respective areas between the adjacent transistors in the first device layer (see, e.g., Fig. 2C)
Regarding Claim 19, Song (see, e.g., Fig. 2C) shows that the plurality of gate isolation regions respectively comprise at least one dielectric layer (e.g., 248) disposed between a gate contact (e.g., 122) of the plurality of gate contacts and a gate structure (e.g., 112) of the second device layer.
Regarding Claim 20, Song (see, e.g., Fig. 2C) shows a plurality of additional gate isolation regions (e.g., insulating layer regions 226) disposed through respective gate structures (e.g., gate electrodes 110) of the first device layer, wherein the plurality of additional gate isolation regions are offset from the plurality of gate isolation regions.
Allowable Subject Matter
Claims 2, 4-9, 11, 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor devices with stacked transistors including gate electrodes having contacts thereto, and having some aspects similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
Prosecution Insights