Prosecution Insights
Last updated: August 17, 2026
Application No. 18/596,869

SEMICONDUCTOR PACKAGE BONDING TOOL AND SEMICONDUCTOR PACKAGE FABRICATION METHOD USING THE SAME

Non-Final OA §102§103
Filed
Mar 06, 2024
Priority
Sep 05, 2023 — RE 10-2023-0117671
Examiner
STONER, KILEY SHAWN
Art Unit
4100
Tech Center
4100
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
1164 granted / 1440 resolved
+20.8% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
41 currently pending
Career history
1486
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
45.5%
+5.5% vs TC avg
§102
27.4%
-12.6% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1440 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group I (claims 1-14) in the reply filed on 7/20/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 8-11 and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Caplet (US2022/0181512A1). With respect to claim 8, Caplet teaches a semiconductor package bonding tool (title; and figures), comprising: a bonding plate (200); and a bonding block (100) disposed on a bottom surface of the bonding plate, wherein the bonding plate includes a first vacuum hole (205) that vertically penetrates the bonding plate, wherein the bonding block includes a bonding stage (101) disposed below the first vacuum hole, and wherein the bonding stage includes: a connection hole (103) connected (broadest reasonable interpretation) to the first vacuum hole (205) and vertically penetrating the bonding stage (figures 1A-5B); and a trench hole (the cavity formed by bosses 107) upwardly recessed from a bottom surface of the bonding stage, and wherein the trench hole surrounds the connection hole (103) and is spaced apart in a horizontal direction from the connection hole (figures 1A-5B; and paragraphs 41-71). With respect to claim 9, Caplet teaches wherein the trench hole (the cavity formed by bosses 107) has a tetragonal frame shape (rectangular) (figures 1A-5B; and paragraphs 41-71). With respect to claim 10, Caplet teaches wherein the trench hole is not connected to the first vacuum hole, and wherein a portion of the bonding stage separates the trench hole and the connection hole (figures 1A-5B; and paragraphs 41-71). With respect to claim 11, Caplet teaches wherein a thickness in a vertical direction of the trench hole is less than a thickness in the vertical direction of the bonding stage (figures 1A-5B). With respect to claim 13, Caplet teaches a plurality of bonding stages (the stages formed by bosses 107) including the bonding stage (101), and the plurality of bonding stages are spaced apart from each other in the horizontal direction on the bottom surface of the bonding plate (figures 1A-5B; and paragraphs 41-71). With respect to claim 14, Caplet teaches wherein a width of the connection hole (103) is less than a width of the first vacuum hole (205) (figure 2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Caplet. With respect to claim 12, Caplet discusses the lateral dimensions of the bonding stage (101) and microchips (paragraphs 42-43), but is silent with respect to a length in the horizontal direction of the trench hole. However, it is the examiner’s position that the horizontal length of the trench hole is merely an obvious design choice based on the microchips being handled and bonded. Thus, the artisan would have been motivation to utilize a horizontal length of the trench hole that is in a range of about 5 mm to about 15 mm in order to ensure that the microchips are precisely gripped by vacuum suction without interference. Allowable Subject Matter Claims 1-7 are allowed. The examiner considers US2022/0181512A1 to be the closest prior art of record; however, the prior art of record does not teach or suggest either alone or in combination a semiconductor package bonding tool as recited by claim 1, particularly a bonding plate (200); and a plurality of bonding blocks (the structures formed by bosses 107) disposed on a bottom surface of the bonding plate, wherein each of the plurality of bonding blocks includes a bonding stage disposed below a respective first vacuum hole of the plurality of first vacuum holes, and wherein the bonding stage includes: a trench hole upwardly recessed from a bottom surface of the bonding stage; and a connection hole connecting a top surface of the bonding stage to the trench hole; and wherein a length in a horizontal direction of the trench hole is greater than a length in the horizontal direction of the connection hole. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KILEY SHAWN STONER whose telephone number is (571)272-1183. The examiner can normally be reached on Monday-Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached on 571-272-3458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KILEY S STONER/ Primary Examiner, Art Unit 1735
Read full office action

Prosecution Timeline

Mar 06, 2024
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §102, §103
Aug 13, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
96%
With Interview (+15.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1440 resolved cases by this examiner. Grant probability derived from career allowance rate.

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