Prosecution Insights
Last updated: April 19, 2026
Application No. 18/596,923

HIGHLY EFFICIENT MICRODEVICES

Non-Final OA §103§112
Filed
Mar 06, 2024
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Vuereal Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
532 granted / 723 resolved
+5.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 723 resolved cases

Office Action

§103 §112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 3, 5-8, 12 and 13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 3, the limitation “adjusted based on an operation range of the vertical device and a peak efficiency of the vertical device” renders the metes and bounds of the claim indefinite as it is impossible to determine the reason for any element in an allegedly infringing device to be adjusted, making infringement impossible to determine. Regarding Claim 5, a conductive layer has already been introduced in superseding Claim 1. The conductive layer is the gate of a vertical transistor, rendering the addition of the “gate electrode” duplicative. Furthermore, in the instant Fig. 2G for example, the gate electrode 268 is on the gate dielectric 218 rather than the passivation layer 266. Regarding Claim 7, it is unclear what the “second passivation layer” with respect to the “passivation layer” in superseding Claim 1. It is assumed to be “passivation layer” 266. Only one such passivation layer is shown in the instant figures. Regarding Claim 8, it is unclear what “the device electrode comprises a separate electrode or a part of nano-contacts” means. Regarding Claims 6, 12 and 13, a single claim which claims both an apparatus and the method steps of using the apparatus is indefinite (MPEP 2173.05(p)). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 4 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over “Monolithic integration of enhancement-mode vertical driving transistors on a standard InGaN/GaN light emitting diode structure” by Lu et al. (Lu) in view of U.S. Pat. Pub. No. 20140353593 to Smets. Regarding Claim 1, Lu teaches in Fig. 1 at least, a vertical device comprising: a plurality of planar active layers LED Epi/ Regrowth formed on a substrate Sapphire, at least one of a top layer of the plurality of planar active layers is formed as a plurality of nano-pillars (Regrowth; although only one is shown it would be obvious to multiply to vary light color and/or intensity); and wherein a part of the sidewalls of the nano-pillars is covered by a dielectric layer Al2O3 and a conductive layer G forming a vertical transistor in series with the vertical device, and wherein the vertical transistor controls current going through the vertical device (see Fig. 1). Lu does not explicitly teach a first passivation layer formed on a space between the plurality of nano-pillars and at least a part of sidewalls of the plurality of nano-pillars. However, in analogous art, Smets teaches a passivation layer 110 between vertical transistors in Fig. 1 at least. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Smets to provide protection to the vertical transistors. Regarding Claim 2, Lu and Smets teach the vertical device of claim 1, further comprising: an ohmic contact layer S formed on a top surface of at least one nano-pillar to create nano-contacts. Regarding Claim 4, Lu and Smets teach the vertical device of claim 1, wherein the dielectric layer and the conductive layer are configured to spread a current to other areas of the vertical device (to the LED for example), wherein the conductive layer acts as a gate of a field-effect transistor G. Regarding Claim 7, Lu and Smets teach the vertical device of claim 1, further comprising: a second passivation layer 110 (see above rejection under 112b) formed over the gate electrode; and a device electrode 103 formed over the second passivation layer to create a functional area for the vertical device, wherein the device electrode comprises one of: a filler layer or a reflector (metal is a reflector). Regarding Claim 8, Lu and Smets teach the vertical device of claim 7, wherein the device electrode comprises a separate electrode S or a part of nano-contacts. Regarding Claim 9, Lu and Smets teach the vertical device of claim 1, wherein the plurality of the nano-pillars are etched down to the plurality of planar active layers formed on the substrate (product by process limitations bear no weight, MPEP 2113). Regarding Claim 10, Lu and Smets teach the vertical device of claim 1, wherein a surface treatment is provided to the first passivation layer to expose defective areas underneath the nano-pillars and remove the nano-pillars placed on the defective areas (product by process limitations bear no weight, MPEP 2113). Regarding Claim 11, Lu and Smets teach the vertical device of claim 1, wherein a surface treatment is provided to the space between the nano-pillars or the sidewalls of the nano-pillars prior to the formation of the first passivation layer to expose defective areas using a chemical etch or a dry plasma etch process (product by process limitations bear no weight, MPEP 2113). Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu and Smets as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20070077670 to Kim et al. (Kim). Regarding Claims 13 and 14, Lu and Smets teach the vertical device of claim 1, but do not teach a filler layer formed on a top surface of the first passivation layer, the filler layer includes one of: a polymer, a solgel, and a dielectric wherein the filler layer further includes a color conversion layer. However, in analogous prior art, Kim teaches a filler 41 that is a polymer [0033] having color conversion capability [0040]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Kim to vary colors of light emitted by the LEDs of Lu. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 06, 2024
Application Filed
Mar 14, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 723 resolved cases by this examiner. Grant probability derived from career allow rate.

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