Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-23 are rejected under 35 U.S.C. 103 as being unpatentable over Dono et al. (US Pub # 2018/0293128) in view of Kim et al. (US Pub # 2022/0100395).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Dono et al. teach a semiconductor device comprising: a memory circuit comprising a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after a start of a read operation during a test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116 where each bank 0..n are mats, identical to a data sequence of pattern data during DM mode) and configured to output a fail address comprising error information of the first read data; and a data processing circuit configured to output the first read data as data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116 where read data DQ includes error / fail address).
Even though Dono et al. teach read data which includes error and error correction done to correct error in the memory device but silent exclusively about configured to generate fail location information by encoding the fail address and wherein the fail location information is a signal for detecting failure locations for the plurality of mats.
Kim et al. teach generate fail location information by encoding the fail address and wherein the fail location information is a signal for detecting failure locations for the plurality of mats (see Fig.7 and paragraph 0093-0100, 0111-0112, claim 15, where error / fail address signal includes fail location of banks / mats).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim et al. to the teaching of Dono et al. where error / fail address of Dono et al. actually include fail location of banks / mats including rows in order to repair identified fail and to reduce redundant costs of having low risk bit error (see Kim et al., paragraph 0030, 0034)
Further reason to combine the teachings of Don and Kim is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards identify error / fail including error / fail address location of memory device.
Regarding claim 2, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dono et al. further teach, wherein the memory circuit is configured to store, in the plurality of mats, write data having a data sequence identical to the data sequence of the pattern data during the test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0112).
Regarding claim 3, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dono et al. further teach, wherein the data processing circuit is configured to generate the fail location information when the pattern data is different from the first read data during the test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111).
Regarding claim 4, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dono et al. further teach, wherein: during the test operation mode operation, the plurality of mats each outputs, as the first read data, write data having a data sequence identical to the data sequence of the pattern data after the start of the read operation; and the plurality of mats each outputs the fail address comprising the error information of the first read data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109).
Regarding claim 5, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dono et al. further teach, wherein the data processing circuit comprises: an input and output sense amplifier configured to generate input data based on the first read data; a latch circuit configured to generate storage data by storing the pattern data when a test mode command is enabled; a flag signal generation circuit configured to generate a flag signal after comparing the input data and the storage data; a data inversion control circuit configured to output the input data as the data when the flag signal is enabled; and a fail location information generation circuit configured to generate the fail location information by encoding the fail address when the flag signal is enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0114).
Regarding claim 6, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dono et al. further teach, wherein: the memory circuit is configured to output second read data and third read data that are stored in the plurality of mats by correcting errors of the second read data and the third read data after a start of read operations that are consecutively performed during a data bus inversion operation; and the data processing circuit is configured to output the third read data as the data by inverting the third read data when a comparison between the second read data and the third read data results in a quantity of differing data by a set quantity or more during the data bus inversion operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116).
Regarding claim 7, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Dono et al. further teach, wherein the data processing circuit comprises: an input and output sense amplifier configured to generate input data based on the second read data and the third read data during the data bus inversion operation; a latch circuit configured to generate storage data by storing the input data when a data bus inversion command is enabled; a flag signal generation circuit configured to generate a flag signal as enabled when a comparison between the input data and the storage data results in a quantity of differing data by the set quantity or more; and a data inversion control circuit configured to output, as the data, the input data that are generated from the third read data by inverting the input data when the flag signal is enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0112).
Regarding independent claim 8, Dono et al. teach a semiconductor system comprising: a controller configured to output a command address during a data bus inversion operation, configured to receive data, configured to output the command address and pattern data during a test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116 where data bus inversion done in DBI mode operation); and a semiconductor device configured to output second read data as the data by inverting or not inverting the second read data based on a comparison between first read data and second read data after a start of read operations that are consecutively performed during a data bus inversion operation based on the command address (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116), configured to output third read data as the data after the start of the read operation during the test operation mode operation based on the command address, and configured to output a fail address comprising error information of the third read data as the fail location information by encoding the fail address when the third read data and the pattern data are different.
Even though Dono et al. teach read data which includes error and error correction done to correct error in the memory device but silent exclusively about configured to receive fail location information and wherein the fail location information is a signal for detecting failure locations for the plurality of mats.
Kim et al. teach configured to receive fail location information and wherein the fail location information is a signal for detecting failure locations for the plurality of mats. (see Fig.7 and paragraph 0093-0100, 0111-0112, claim 15, where error / fail address signal includes fail location of banks / mats).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim et al. to the teaching of Dono et al. where error / fail address of Dono et al. actually include fail location of banks / mats including rows in order to repair identified fail and to reduce redundant costs of having low risk bit error (see Kim et al., paragraph 0030, 0034)
Further reason to combine the teachings of Don and Kim is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards identify error / fail including error / fail address location of memory device.
Regarding claim 9, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Dono et al. further teach, wherein the controller is configured to detect fail locations within a plurality of mats that are included in the semiconductor device based on the fail location information (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0108).
Regarding claim 10, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Dono et al. further teach, wherein the semiconductor device comprises: a command generation circuit configured to generate a read command, a data bus inversion command, and a test mode command by decoding at least part of the command address that is input in synchronization with a clock (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094); an address generation circuit configured to generate a plurality of mat addresses that are all enabled when the data bus inversion command and the test mode command are enabled; a memory circuit comprising a plurality of mats and configured to output the first read data and the second read data that are stored in the plurality of mats that are selected based on the plurality of mat addresses when the read command is enabled, configured to output the third read data that are stored in the plurality of mats based on the plurality of mat addresses (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109), and configured to output the fail address; and a data processing circuit configured to output the second read data as the data by inverting the second read data when a comparison between the first read data and the second read data results in a quantity of differing data by a set quantity or more when the data bus inversion command is enabled, configured to output the third read data as the data when the test mode command is enabled, and configured to generate the fail location information by encoding the fail address (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0115).
Regarding claim 11, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Dono et al. further teach, wherein the memory circuit is configured to store write data having a data sequence identical to a data sequence of the pattern data during the test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0107).
Regarding claim 12, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Dono et al. further teach, wherein the data processing circuit is configured to generate the fail location information when the pattern data and the third read data are different during the test operation mode operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111).
Regarding claim 13, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Dono et al. further teach, wherein: each of the plurality of mats is configured to output the first read data and the second read data after the start of the read operations that are consecutively performed during the data bus inversion operation; the plurality of mats each is configured to output write data as the third read data after the start of the read operation during the test operation mode operation; and the plurality of mats each is configured to output the fail address comprising error information of the third read data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0107).
Regarding claim 14, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Dono et al. further teach, wherein the data processing circuit comprises: an input and output sense amplifier configured to generate input data based on the data identical with the pattern data that are input after a start of a write operation during the test operation mode operation and configured to generate the input data based on the first read data, the second read data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092) and the third read data after the start of the read operation; a latch circuit configured to generate storage data by storing the input data that are generated from the first read data when the data bus inversion command is enabled and configured to generate the storage data by storing the pattern data when the test mode command is enabled; a flag signal generation circuit configured to generate a flag signal by comparing the input data and the storage data based on the data bus inversion command and the test mode command (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094); a data inversion control circuit configured to generate write data from the input data after a start of a write operation during the test operation mode operation, configured to output the input data as the data by inverting the input data when the flag signal is enabled after the start of the read operation during the data bus inversion operation, and configured to output the input data as the data when the flag signal is enabled after the start of the read operation during the test operation mode operation; and a fail location information generation circuit configured to generate the fail location information by encoding the fail address when the flag signal is enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0115).
Regarding claim 15, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Dono et al. further teach, wherein the flag signal generation circuit comprises: a comparison circuit configured to generate comparison data by comparing the input data and the storage data after the start of the read operation during the data bus inversion operation and the test operation mode operation; and a detection circuit configured to generate the flag signal as enabled when the comparison data has a quantity of differing data that is a preset quantity or more when the data bus inversion command is enabled and configured to generate the flag signal as enabled when the comparison data indicates differing data when the test mode command is enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116).
Regarding independent claim 16, Dono et al. teach a data output method comprising: detecting which of a data bus inversion operation and a test operation mode operation is to be performed based on a command address; performing a data bus inversion operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116, DM and DBI mode) including: generating write data by receiving data after a start of a write operation based on the command address, storing the write data in a plurality of mats based on a plurality of mat addresses that are all enabled, and outputting, as the data, first read data and second read data that are output from the write data by one of inverting and not inverting the first read data and the second read data after a start of a read operation; (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116, output read data DQ) and performing a test operation mode operation including: generating the write data by receiving the data identical with pattern data after the start of the write operation based on the command address, storing the write data in the plurality of mats, and, third read data that are output from the write data and a fail address comprising error information of the third read data by encoding the third read data and the fail address after the start of the read operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116).
Even though Dono et al. teach read data which includes error and error correction done to correct error in the memory device but silent exclusively about outputting, as fail location information and wherein the fail location information is a signal for detecting failure locations for the plurality of mats.
Kim et al. teach outputting, as fail location information and wherein the fail location information is a signal for detecting failure locations for the plurality of mats (see Fig.7 and paragraph 0093-0100, 0111-0112, claim 15, where error / fail address signal includes fail location of banks / mats).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim et al. to the teaching of Dono et al. where error / fail address of Dono et al. actually include fail location of banks / mats including rows in order to repair identified fail and to reduce redundant costs of having low risk bit error (see Kim et al., paragraph 0030, 0034)
Further reason to combine the teachings of Don and Kim is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards identify error / fail including error / fail address location of memory device.
Regarding claim 17, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Dono et al. further teach, wherein: the data bus inversion operation is performed when a data bus inversion command is enabled by decoding at least part of the command address; and the test operation mode operation is performed when a test mode command is enabled by decoding at least part of the command address (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0108).
Regarding claim 18, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Dono et al. further teach, wherein the data bus inversion operation comprises: a data bus inversion write operation including generating the write data by receiving the data when a write command is enabled by decoding at least part of the command address and storing the write data in a mat that is selected by the plurality of mat addresses that are all enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092); a data bus inversion read operation including outputting, as the first read data and the second read data, the write data that are stored in the mat that is selected by the plurality of mat addresses that are all enabled when a read command is enabled by decoding at least part of the command address; and a data inversion operation including outputting the second read data as the data by one of inverting and not inverting the second read data based on a comparison between the first read data and the second read data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111).
Regarding claim 19, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Dono et al. further teach, wherein in the data inversion operation, the second read data are output as the data by inverting the second read data when a comparison between the first read data and the second read data results in a quantity of differing data by a set quantity or more (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0107).
Regarding claim 20, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Dono et al. further teach, wherein the test operation mode operation comprises: a test mode write operation including generating the write data by receiving the data identical with the pattern data when a test mode command is enabled by decoding a first group of the command address and storing the write data in a mat that is selected by the plurality of mat addresses that are all enabled (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089); a test mode read operation including outputting the third read data and a fail address comprising error information of the third read data from the write data that are stored in the mat that is selected by the plurality of mat addresses that are all enabled when a read command is enabled by decoding at least part of the command address; and performing fail location information generation including comparing the pattern data and the third read data and outputting fail location information that is generated by encoding the fail address based on a result of the comparison (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111).
Regarding claim 21, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 20 on which this claim depends.
Dono et al. further teach, wherein the fail location information generation includes ouputting the fail location information that is generated by encoding the fail address when a comparison between bits that are included in the pattern data and bits that are included in the third read data results in at least one different bit (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109).
Regarding independent claim 22, Dono et al. teach a method comprising: comparing first read data and pattern data resulting in comparison data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116, comparing is done during read operation); and when the first read data is different from the pattern data, performing a test operation mode operation including: outputting the first read data, outputting a fail address comprising error information of the first read data (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0109, 0111-0116 where read data DQ includes error / fail info or address).
Even though Dono et al. teach read data which includes error and error correction done to correct error in the memory device but silent exclusively about generating fail location information by encoding the fail address and wherein the fail location information is a signal for detecting failure locations for the plurality of mats.
Kim et al. teach generating fail location information by encoding the fail address and wherein the fail location information is a signal for detecting failure locations for the plurality of mats. (see Fig.7 and paragraph 0093-0100, 0111-0112, claim 15, where error / fail address signal includes fail location of banks / mats).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim et al. to the teaching of Dono et al. where error / fail address of Dono et al. actually include fail location of banks / mats including rows in order to repair identified fail and to reduce redundant costs of having low risk bit error (see Kim et al., paragraph 0030, 0034)
Further reason to combine the teachings of Don and Kim is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards identify error / fail including error / fail address location of memory device.
Regarding claim 23, Dono et al. teach all claimed subject matter as applied in prior rejection of claim 22 on which this claim depends.
Dono et al. further teach, further comprising performing a data bus inversion operation including comparing first read data and second read data resulting in comparison data and outputting the first read data and second read data by one of inverting and not inverting the first read data and the second read data based on the comparison data after a start of a read operation (see Fig. 1-8, 11-16 and paragraph 0026-0027, 0030-0037, 0039-0042, 0044-0055, 0057-0066, 0089-0092, 0094-0108).
Response to Arguments
Applicant's arguments filed 11/26/2025 have been fully considered but they are moot in view of the new ground(s) of rejection.
Conclusion
Applicant amendment necessitated the new ground of rejection presented in this office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824