DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Choi et al. (US PG-Pub No.: 2007/0128846 A1, hereinafter, “Choi”), prior art of record, in view of Tsai (US PG-Pub No.: 2020/0411654 A1, hereinafter, “Tsai”).
Regarding claim 1, Choi discloses a memory device (see Choi, FIG. 10), comprising:
A semiconductor substrate (100, ¶ [0004]) having a recess recessed from a top surface thereof (FIG. 10);
a first high-k gate dielectric layer (120, ¶ [0052]) disposed in the semiconductor substrate (100), wherein the first high-k gate dielectric layer (120) is partially disposed in the recess to define a lower portion below the top surface of the semiconductor substrate (100) and an upper portion above the top surface of the semiconductor substrate (100), such that a top surface of the first high-k gate dielectric layer (120) is higher than the top surface of the semiconductor substrate (100);
a first metal gate electrode layer (160, ¶ [0064]) disposed over the first high-k gate dielectric layer (120), wherein a lower portion of the first metal gate electrode layer (160) is surrounded by the first high-k gate dielectric layer (120), and wherein a width of an upper portion of the first metal gate electrode layer (160) is greater than a width of the lower portion of the first metal gate electrode layer (160, FIG. 10); and
a first dielectric portion (162, ¶ [0065]) disposed over the first metal gate electrode layer (160, FIG. 10).
Choi is silent regarding that a width of the lower portion of the first high-k gate dielectric layer is equal to a width of the upper portion of the first high-k gate dielectric layer.
Tsai, however, discloses a memory device (see Tsai, FIG. 4), wherein a width of a lower portion of a first high-k gate dielectric layer (340, ¶ [0043]) is equal to a width of an upper portion of the first high-k gate dielectric layer (340, FIG. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Choi’s width of the lower portion of the first high-k gate dielectric layer equal to a width of the upper portion of the first high-k gate dielectric layer, as taught by Tsai, since it is an alternative design.
Regarding claim 2, Choi in view of Tsai discloses the memory device of claim 1, wherein the first metal gate electrode layer (160) is in direct contact with the top surface of the first high-k gate dielectric layer (in order to meet the claim limitation, the first high-k gate dielectric layer is 150; Choi, FIG. 10), wherein the first high-k gate dielectric layer (150) is in direct contact with a surface of the recess of the semiconductor substrate (100, FIG. 10).
Regarding claim 3, Choi in view of Tsai discloses the memory device of claim 1, wherein the first metal gate electrode layer (160) is separated from the semiconductor substrate (100) by the first high-k gate dielectric layer (120; Choi, FIG. 10).
Regarding claim 4, Choi in view of Tsai discloses the memory device of claim 1, wherein the first high-k gate dielectric layer (120) is separated from the first dielectric portion (162) by the first metal gate electrode layer (160; Choi, FIG. 10).
Regarding claim 5, Choi in view of Tsai discloses the memory device of claim 1, wherein the top surface of the semiconductor substrate (100) is higher than a bottom surface of the lower portion of the first metal gate electrode layer (160; Choi, FIG. 10).
Regarding claim 6, Choi in view of Tsai discloses the memory device of claim 1, wherein a top surface of an upper portion of the first metal gate electrode layer (160) is higher than the top surface of the first high-k gate dielectric layer (120; Choi, FIG. 10).
Regarding claim 8, Choi in view of Tsai discloses the memory device of claim 1, wherein the width of the upper portion of the first metal gate electrode layer (160) is substantially the same as a width of the first dielectric portion (162; Choi, FIG. 10).
Claims 7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over by Choi et al. (US PG-Pub No.: 2007/0128846 A1, hereinafter, “Choi”), prior art of record, in view of Tsai (US PG-Pub No.: 2020/0411654 A1, hereinafter, “Tsai”), as applied to claim 1 above, further in view of Zhu (WO 2014/169506 A1, hereinafter, “Zhu”).
Regarding claim 7, Choi in view of Tsai discloses the memory device of claim 1.
Choi in view of Tsai is silent regarding that the width of the upper portion of the first metal gate electrode layer is substantially the same as the width of the lower portion of the first high-k gate dielectric layer and is the same as the width of the upper portion of the first high-k gate dielectric layer.
Zhu, however, discloses a memory device (see Zhu, FIG. 21), wherein a width of an upper portion of a first metal gate electrode layer (1020, FIG. 21) is substantially the same as a width of a lower portion of a first high-k gate dielectric layer (1016, FIG. 21) and is the same as a width of an upper portion of the first high-k gate dielectric layer (1016, FIG. 21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form the width of the upper portion of the first metal gate electrode layer of Choi in view of Tsai substantially the same as the width of the lower portion of the first high-k gate dielectric layer and is the same as the width of the upper portion of the first high-k gate dielectric layer, as taught by Zhu, since it is an alternative design.
Regarding claim 9, Choi in view of Tsai discloses the memory device of claim 1, wherein a sidewall of the first high-k gate dielectric layer (120) is vertically aligned to a sidewall of the upper portion of the first metal gate electrode layer (160) in a cross-sectional view of the memory device (FIG. 10).
Choi in view of Tsai is silent regarding that the sidewall of the first high-k gate dielectric layer is vertically aligned to a sidewall of the recess of the semiconductor substrate.
Zhu, however, discloses a memory device (see Zhu, FIG. 21), wherein a sidewall of a first high-k gate dielectric layer (1016, FIG. 21) is vertically aligned to a sidewall of a recess of a semiconductor substrate (1000, FIG. 21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form the sidewall of the first high-k gate dielectric layer of Choi in view of Tsai vertically aligned to a sidewall of the recess of the semiconductor substrate, as taught by Zhu, since it is an alternative design.
Regarding claim 10, Choi in view of Tsai and Zhu discloses the memory device of claim 9, wherein the sidewall of the upper portion of the first metal gate electrode layer (160) is vertically aligned to a sidewall of the first dielectric portion (162) in the cross-sectional view of the memory device (Choi, FIG. 10).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over by Choi et al. (US PG-Pub No.: 2007/0128846 A1, hereinafter, “Choi”), prior art of record, in view of Tsai (US PG-Pub No.: 2020/0411654 A1, hereinafter, “Tsai”), as applied to claim 1 above, further in view of Chuang et al. (US PG-Pub No.: 2010/0019344 A1, hereinafter, “Chuang”), prior art of record.
Regarding claim 11, Choi in view of Tsai discloses the memory device of claim 1.
Choi in view of Tsai is silent regarding a planar gate structure, wherein the first high-k gate dielectric layer and the first metal gate electrode layer form a recessed gate structure in a peripheral circuit region of the memory device and adjacent to the planar gate structure.
Chuang, however, discloses a memory device (see Chuang, FIG. 5), comprising a first high-k gate dielectric layer (252, ¶ [0022]) and a first metal gate electrode layer (254+256, ¶ [0022]) form a recessed gate structure in a peripheral circuit region of a memory device and adjacent to a planar gate structure (220, FIG. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form a planar gate structure, wherein the first high-k gate dielectric layer of Choi in view of Tsai and the first metal gate electrode layer form a recessed gate structure in a peripheral circuit region of the memory device and adjacent to the planar gate structure, as taught by Chuang, in order to form an additional passive region for the memory device.
Allowable Subject Matter
Claims 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 12, in particular, the planar gate structure comprises: a second high-k gate dielectric layer disposed on and in contact with the top surface of the semiconductor substrate; a second metal gate electrode layer disposed over the second high-k gate dielectric layer; and a second dielectric portion disposed over the second metal gate electrode layer; wherein a top surface of the second high-k gate dielectric layer is coplanar with the top surface of the first high-k gate dielectric layer; wherein a top surface of the second metal gate electrode layer is coplanar with a top surface of the first metal gate electrode layer; wherein a top surface of the second dielectric portion is coplanar with a top surface of the first dielectric portion. Claims 13-15 depend upon claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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/XIA L CROSS/Primary Examiner, Art Unit 2892
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