Prosecution Insights
Last updated: August 17, 2026
Application No. 18/597,074

TRANSISTOR

Non-Final OA §103
Filed
Mar 06, 2024
Priority
Sep 07, 2021 — JP 2021-145463 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Japan Display Inc.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
3m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
507 granted / 815 resolved
-5.8% vs TC avg
Strong +24% interview lift
Without
With
+24.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
59 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species A represented by figure 1, and claims 1-3 and 5-8 in the reply filed on July 2, 2026 is acknowledged. Accordingly, claims 4, and 9-20 are withdrawn from consideration. Claim 5 is withdrawn from consideration as it requires a crystalline insulating layer. This claim is drawn to figure 6. Figure 6 was listed as Species F. Species F was not elected. Claim 6 is withdrawn from consideration as it requires the conductive alignment layer to be separated into parts as shown in figure 7A. Figure 7A was listed as Species G. Species G was not elected. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on March 6, 2024; and February 26, 2025 were considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2013/0032816 A1) (“Hwang”). Regarding claim 1, Hwang teaches at least in figures 1-4: an amorphous substrate (26; ¶ 0036, where 26 may include an oxide, and oxides are known to be amorphous. Thus, it would have been obvious that the oxide substrate disclosed in Hwang would be amorphous); a conductive alignment layer (24) over the amorphous substrate (26); a heterojunction structure (34/36) comprising a semiconductor layer (¶ 0037, where 34 comprises AlGan, or Gan) and a polarization layer (36) in contact with the semiconductor layer (34), over the conductive alignment layer (24); and a gate electrode (38G) over the heterojunction structure (34/36), wherein the heterojunction structure (34/36) comprises a recessed portion in a region overlapping the gate electrode (the region occupied by 42 is the recessed portion). Regarding claim 2, Hwang teaches at least in figures 1-4: wherein a gate insulating layer (42) is provided in the recessed portion (42 is formed in the recessed portion). Regarding claim 3, Hwang teaches at least in figures 1-4: wherein the recessed portion (area occupied by 42) is provided in the polarization layer (36). Regarding claim 8, Hwang teaches at least in figures 1-4: wherein the amorphous substrate (26) is an amorphous glass substrate (oxide is known in the art as glass. The most common oxide is silicon oxide and is also known as a glass. Further, as stated in claim 1 silicon oxide, i.e. glass, is known to be amorphous. Therefore, it would have been obvious to one of ordinary skill in the art that when Hwang teaches the substrate may be an oxide it is known that it could be silicon oxide, and it would have been obvious that silicon oxide, which is also known as glass, would be amorphous.). Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang, in view of Watahiki et al., "Preparation of AIGaN/GaN HEMT structures on amorphous substrates with graphene buffer layers", Proceedings of the 64th JSAP Spring Meeting 2017, March 1, 2017, 17a-503-2 (“Watahiki”). Regarding claim 7, Hwang does not teach wherein the conductive alignment layer (24) comprises at least one selected from titanium, graphene, and zinc oxide. This is because Hwang teaches: The conductive alignment layer 24 comprises Al, Cu, Au, and/or Si. Watachiki teaches: wherein the conductive alignment layer (the buffer layer used to grow the heterojunction structure on) comprises at least one selected from titanium, graphene, and zinc oxide (pg. 1 at experimental method). It would have been obvious to one of ordinary skill in the art to replace the material of Hwang with the material of Watachiki because Watachiki teaches that by using graphene as it makes it easier to achieve nitride crystal growth on a glass substate because of the low softening temperature of the substrate. One would be motivated to combine the references as it would allow for one to fabricate the device of Hwang less expensively as stated in Watachiki. One also gains the additional benefit that no surface roughness occurs with the formation of the heterojunction structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 06, 2024
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
86%
With Interview (+24.3%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allowance rate.

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