DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 2 and 9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the self-referencing circuit comprises: a plurality of second memory cells each having a control gate to which a tuning gate voltage is applied, the second memory cells being connected to each other in parallel; and a comparator configured to output a comparison result between a voltage across opposite ends of the plurality of second memory cells and a preset comparator voltage as a digital signal; while in regard to claim 9, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the self-referencing circuit comprises: a plurality of second memory cells each having a control gate to which a tuning gate voltage is applied, the second memory cells being connected to each other in parallel; and a comparator configured to output a comparison result between a voltage across opposite ends of the plurality of second memory cells and a preset comparator voltage as a digital signal.
Claim(s) 3-5 and 10-12 depend from claim(s) 2 and 9, and as such are also objected for the same reason.
Claim Objections
Claim(s) 15 is objected to because of the following: the claim seems to be missing language of the type “non-transitory.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-8 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by 20180114569 to Strachan et al. (“Strachan”).
As to claim 1, Strachan teaches a neural network system (As found in at least the Abstract, at least FIGS. 1-5, at least [0010])comprising: a neural network circuit comprising first memory cells arranged in an array (As found in at least FIGS. 1-3); and a self-referencing circuit electrically connected to a row line or a column line of the neural network circuit and configured to apply current to the connected row line or column line so that a plurality of target memory cells have preset target weights (As found in at least FIG. 2 and at least [0042]: 220 receives a threshold voltage (by Ohms current Law: V = I * R, where there is a voltage, there is a current), a voltage/current 223 is applied to a connected row line 220, which includes a plurality of memory cells 221; and as found in at least claim 9: “the memory cells not coupled to the threshold row line are programmed according to a weight matrix; the memory cells coupled to the threshold row line are programmed according to a threshold current for a corresponding column line), wherein the target memory cells comprise all memory cells positioned on the row line or the column line to which the self-referencing circuit is connected (As found in at least FIG. 2: the entire row is a target).
As to claim 6, Strachan teaches further comprising a write circuit configured to perform a programming operation on the target memory cells so that the target memory cells have the preset target weights (As found in at least the Abstract).
As to claim 7, while Strachan relevantly teaches such claimed reference or constat voltage, as in [0042]; a band gap circuit to provide a reference voltage has been in use for decades, nothing new here; official notice: at least US 7031191 discloses in ample detail bandgap circuit generates voltage reference.
As to claim 8, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
As to claim 13, see rejection to at least claim 6.
As to claim 14, see rejection to at least claim 7.
As to claim 15, Strachan teaches A computer-readable recording medium having recorded thereon a program to cause the method of claim 8 to be executed on a computer (As found in at least [0039]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights