DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7, in the reply filed on July 2, 2026 is acknowledged. Accordingly, Claims 8-15 are withdrawn from consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on
January 28, 2026; December 24, 2025; September 16, 2025; August 6, 2025;
February 4, 2025; January 28, 2025; January 10, 2025; and March 6, 2024.
Were considered by the examiner.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-5 are rejected under scope of enablement detailed in Trustees of Boston Univ. v. Everlight Elec. Co., Ltd., 896 F.3d 1357 (Fed. Cir. 2018). In Trustees of Boston Univ. the Court stated “[T]o be enabling, the specification of a patent must teach those skilled in the art how to make and use the full scope of the claimed invention without ‘undue experimentation.’ ” Id. at 1362 (citations omitted). The Court further elaborated and stated “[] the inquiry is not whether it was, or is, possible to make the full scope of the claimed device—a scope that here covers a monocrystalline growth layer directly on an amorphous layer. The inquiry is whether the patent’s specification taught one of skill in the art how to make such a device without undue experimentation as of the patent’s effective filing date. Id. at 1364. The Court went on to explain that one must disclose how to make the full scope of the invention for the claims to be enabled. Here, Applicant does not enable the full scope of the claim.
To determine this Examiner will use the Wands factors under MPEP 2164.01(a).
Breath of the claims. The claims cover every single oxide semiconductor known now and in the future along with every etching solution known now and in the future.
Nature of the Invention. The invention is directed to a polycrystalline oxide semiconductor layer.
State of the Prior Art. The state of the prior art is evidenced by the art of record.
Level of One of Ordinary Skill in the Art. This is evidenced by the prior art of record and to will be determined by a competent court in the future.
Amount of Direction Provided by the Inventor. In ¶ 0046 appears to list some etchants. This list is not a closed list, nor does Applicant state these are the only etchants that will work. In addition, Applicant does not state which of these, if any, will meet the claim limitation.
Amount of Direction Provided by the Inventor. There is some direction in ¶ 0046 as to what etchants to use, but there is no direction in how to determine, without experimentation, the expanse of the claim without undue experimentation. Nor is there direction on which etchant and which oxide semiconductor combination will work to meet the claim limitation.
Existence of Working Examples. Examiner was unable to find where an oxide semiconductor and etchant combination where shown to work together to meet the claim limitation.
Quantity of Experimentation Needed to Make or Use the Invention Based on the Content of the Disclosure. One of ordinary skill in the art would need to recreate the device of the Applicant and individually test each and every etchant not listed in ¶ 0046.
Based upon the above, and based upon the Board of Trustees decision it is Examiner’s position that Applicant has not enabled the full scope of the claim. Further, the scope of Applicant’s claims in light of the disclosure leaves gaps that are to wide and do not constitute an enabling disclosure for the entirety of scope of the claim language. The combinations of oxide semiconductor and etchants are to vast a ravine to traverse on an artisan’s knowledge of the prior art. Id. at 1364.
Regarding claim 3,
Claim 3 list some etchants, but does not list the oxide semiconductors. Therefore, one will still need to perform undue experimentations to meet the claim limitation.
Regarding claim 4,
Claim 4 is rejected for the same reasons as claims 2-3 above. In claim 4 Applicant has shifted from an wet etch to a gas etch, but does not state which oxide semiconductor material and what gat etchant are to be used together.
Regarding claim 5,
Claim 5 list fluorine as the gas etchant, but require undue experimentation for the same reason as claim 3 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al. (US 2017/0236842 A1) (“Matsuda”), in view of Chiang et al. (US 2005/0199959 A1) (“Chiang”), in view of Nakazawa et al. (US 2020/0335609 A1) (“Nakazawa”).
Regarding claim 1, Matsuda teaches at least in figures 1A-2C:
a gate electrode (105_1);
a gate insulating layer (106-108) over the gate electrode (105_1);
an oxide semiconductor layer (109_1a-1b; collectively 109) having a polycrystalline structure (¶ 0181, where 109 can be polycrystalline and an oxide semiconductor) over the gate insulating layer (106-108);
a source electrode (110_1a) and a drain electrode (110_1b) over the oxide semiconductor layer (109); and
wherein the oxide semiconductor layer (109) comprises a first region overlapping one of the source electrode and the drain electrode (109 below 110_1a-1b) and a second region between the source electrode and the drain electrode (109 between 110_1a-1b), and
a difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm (as shown in figure 2B 109 is flat. Therefore, it is obvious that the film thickness between the first region and second region could be zero).
Matsuda does not teach:
an interlayer insulating layer in contact with the oxide semiconductor layer,
the interlayer insulating layer covering the source electrode and the drain electrode,
The second region in contact with the interlayer insulating layer, and
This is because Matsuda teaches a double gate, a top and bottom gate, transistor.
Chiang teaches at least in figures 1A-1F:
That a double gate transistor is an obvious variant of the bottom gate transistor. It would have been obvious to one of ordinary skill in the art to remove the top gate of Matsuda and create a bottom gate transistor because Chiang teaches these are art recognized obvious variants of each other. Thus, it would have been obvious for one of ordinary skill in the art to apply a known technique to a known device (remove of the top gate) and try this obvious variant as Chiang teaches it is known obvious variant that will yield predictable results. Additionally, one may be motivated to do so as it would simplify processing time of the transistor.
Removing the top gate of Matsuda would result in the top of Matsuda’s transistor looking like the top of Nakazawa’s transistor.
Nakazawa teaches at least in figure 1B:
an interlayer insulating layer (114) in contact with the oxide semiconductor layer (108),
the interlayer insulating layer (114) covering the source electrode (112a) and the drain electrode (112b),
The second region (middle part of 108) in contact with the interlayer insulating layer (114)
Based upon the above, claim 1 would have been obvious to one of ordinary skill in the art.
Regarding claim 2-3, Matsuda teaches at least in figures 1A-2C:
Claims 2-3 do not state what the oxide semiconductor is. Claims 2-3 only require the claimed wet etchant. One of these is hydrofluoric acid. Matusda teaches using hydrofluoric acid to remove the chlorine from the trench 103 which exposes the oxide semiconductor show in figure 8C. ¶ 0309. Therefore, the limitations of claims 2-3 are met.
Regarding claims 4-5, Matsuda teaches at least in figures 1A-2C:
Claims 4-5 do not state what the oxide semiconductor is. Claims 4-5 only require the etchant gas to use fluorine. Figure 8C and ¶ 0305 states that an etching gas can contain fluorine. Therefore, the limitations of claims 4-5 are met.
Regarding claim 6, Matsuda teaches at least in figures 1A-2C:
wherein the film thickness of the first region is greater than or equal to 10 nm and less than or equal to 30 nm (¶¶ 0248 and 250, where 109_1a can be 10nm or smaller, and 109_1b can be 5nm or larger. Therefore, it would have been obvious that the combination of 109_1a and 109_1b could be within the claimed range.).
Regarding claim 7, Matsuda teaches at least in figures 1A-2C:
wherein the oxide semiconductor layer (109) comprises indium and at least one or more metal elements, and a ratio of the indium to the indium and the at least one or more metal elements is greater than or equal to 50% (¶¶ 0229-233, where one can adjust the ratio of In to the at least one or more metal elements such that the claimed ratio is achieved.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VINCENT WALL/Primary Examiner, Art Unit 2898
Prosecution Insights