Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 17th, 2026 has been entered.
Response to Amendment
The amendment filed March 17th, 2026 has been entered. Claims 1-20 are pending in this application. Applicant’s amendments to the claims have overcome each and every objection previously set forth in the Final Office Action mailed January 20th, 2026. The amendments to the claims clarify the identification of the transistors and align the claim terminology with the terminology used in the specification. Accordingly, the prior rejection made under 35 USC § 112(a) based on lack of written description support for the transistor identification has been overcome by the amendment.
The previous rejections set forth in the prior Office action have been withdrawn in light of the claim amendments and applicant’s arguments, which have been found persuasive with respect to the prior art previously relied upon. However, upon further consideration of the amended claims, a new ground(s) of rejection is made under 35 USC § 103, as set described below.
Response to Arguments
Applicant’s arguments, see pages 9-15, filed March 17th, 2026, with respect to the rejection(s) of claims 1-20 under 35 USC § 112(a), and claims 1 & 14 under 35 USC § 103, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
In regards to claims 1 and 14, Examiner agrees with Applicant’s argument that Huang (US 2017/0126214) in view of Zampaglione (US 2007/0252623) fails to teach the first and second transistors connected together in series, as recited in claim 1. In view of the amendments and arguments, the prior rejection based on Huang in view of Zampaglione has been withdrawn. However, upon an updated prior art search and consideration of the amended claims, new prior art has been applied, as set forth below. The newly applied references teach the claimed series transistor configuration and associated control terminal connections as recited in the claims.
Claim Objections
Claim 13 is objected to because of the following informalities:
In claim 13, lines 9-10, it reads “the control terminals of the second, fourth, fifth, and sixth transistors are respective gate terminals”, it should read “the control terminals of the second, fourth, fifth, and second-diode connected transistors are respective gate terminals”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 9,310,435), hereinafter Chen, in view of Ahmadi (US 7,649,395).
Regarding claim 1, Chen teaches a circuit (Chen, Fig. 2), comprising:
a first transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal configured to receive a first input (Chen, Fig. 2, transistor Mp[1]);
a second transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the first transistor to form a series connection between the first transistor and the second transistor, the control terminal configured to receive the first input (Chen, Fig. 2, transistor Mp[2]);
a tenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the second transistor, the control terminal configured to receive a second input (Chen, Fig. 2, transistor Mp[3]);
a ninth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the tenth transistor to form a series connection between the tenth transistor and the ninth transistor, the control terminal configured to receive a third input (Chen, Fig. 2, transistor Mp[4]); and
a eighth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the ninth transistor, the control terminal configured to receive a fourth input (Chen, Fig. 2, transistor Mn[4]).
Chen fails to teach a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the first current conduction terminal of the second diode-connected transistor to form a diode and the second current conduction terminal of the eighth transistor.
However, Ahmadi, in an analogous art, teaches a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the first current conduction terminal of the second diode-connected transistor to form a diode and the second current conduction terminal of the eighth transistor (Ahmadi, Fig. 6, transistor 572; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
Chen and Ahmadi are both considered to be analogous to the claimed invention because both are in the same field of scan flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of having a diode-connected transistor in a circuit made up of transistors that form a series connection.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Regarding claim 2, the combination of Chen in view of Ahmadi teaches the circuit of claim 1, wherein: the first input is a data input; the second input is an inverse scan enable input; the third input is a scan enable input; and the fourth input is a scan data input (Chen, Fig. 2, col. 4, lines 34-38, “The flip-flop 30 may be a scan flip-flop, operate between DC supply voltages Vdd and G [e.g., ground], and have terminals D, SI, SE, CK and Q as a data input terminal, a scan input terminal, a scan enabling terminal”; col. 2, lines 53-55, “a signal [e.g., a second enabling signal] at the terminal SE may be inverted by the inverter 28 and outputted to a terminal SEB [e.g., as a first enabling signal…”).
Regarding claim 4, the combination of Chen in view of Ahmadi teaches the circuit of claim 1, further comprising:
a seventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the tenth transistor (Ahmadi, Fig. 6, transistor 506; transistor 506 equates to a seventh transistor and any transistor that is connected to the same node equates to a tenth transistor); and
a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the a first diode-connected transistor to form a diode and the first current conduction terminal of the seventh transistor (Ahmadi, Fig. 6, transistor 570; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of a transistor and diode-connected transistor being connected.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Regarding claim 5, the combination of Chen in view of Ahmadi teaches the circuit of claim 4, wherein: the control terminal of the seventh transistor is configured to receive a scan data input (Ahmadi, Fig. 11 teaches the gate of transistor 506 being a scan input/scan data input [SI]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of the control terminal of the seventh transistor being configured to receive a scan data input.
The suggestion/motivation for doing so would be to control the signal path of the circuit since transistors are commonly controlled by input signals to control the operation of the circuit.
Regarding claim 6, the combination of Chen in view of Ahmadi teaches the circuit of claim 5, wherein: the first current conduction terminal of the a first diode-connected transistor is configured to receive a voltage from a voltage source (Ahmadi, Fig. 11 teaches transistor 570 as being located in the upper branch that is connected to VDD).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of a current conduction terminal of a diode-connected transistor being configured to receive a voltage from a voltage source.
The suggestion/motivation for doing so would be to provide a biasing, voltage drop or voltage reference functionality in the circuit.
Regarding claim 7, the combination of Chen in view of Ahmadi teaches the circuit of claim 1, further comprising:
a fifth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the first transistor (Chen, Fig. 2, transistor P3); and
a sixth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the second transistor (Chen, Fig. 2, transistor N3).
Regarding claim 8, the combination of Chen in view of Ahmadi teaches the circuit of claim 7, wherein: the control terminal of the fifth transistor is configured to receive a scan enable input (Chen, Fig. 2 teaches an SE gate for transistor P3); and
the control terminal of the sixth transistor is configured to receive an inverse scan enable input (Chen, Fig. 2 teaches an SEB gate for transistor N3).
Regarding claim 9, the combination of Chen in view of Ahmadi teaches the circuit of claim 8, wherein:
the first current conduction terminal of the fifth transistor is configured to receive a voltage from a voltage source (Chen, Fig. 2 teaches transistor P3 being connected to Vdd); and
the second current conduction terminal of the sixth transistor is coupled to ground (Chen, Fig. 2 teaches transistor P3 being connected to G).
Regarding claim 10, the combination of Chen in view of Ahmadi teaches the circuit of claim 1, further comprising:
an eleventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal (Ahmadi, Fig. 11, transistor 504);
a third transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the eleventh transistor (Ahmadi, Fig. 11, transistor 510);
a fourth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the third transistor (Ahmadi, Fig. 11, transistor 512); and
a fourteenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the fourth transistor, and the control terminal coupled to the control terminal of the eleventh transistor and the second current conduction terminal of the tenth transistor (Ahmadi, Fig. 11, transistor 514).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of the transistor stack taught in Ahmadi.
The suggestion/motivation for doing so would be to control signal propagation, delay or voltage levels within the circuit.
Regarding claim 11, the combination of Chen in view of Ahmadi teaches the circuit of claim 10, wherein: the control terminal of the third transistor is configured to receive a clock input (Ahmadi, Fig. 11 teaches an CK gate for transistor 510); and the control terminal of the fourth transistor is configured to receive an inverse clock input (Ahmadi, Fig. 11 teaches an inverse CK gate for transistor 512).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of control terminals of the third and fourth transistors receiving clock and inverse clock signals.
The suggestion/motivation for doing so would be to control switching timing and signal propagation in the circuit.
Regarding claim 12, the combination of Chen in view of Ahmadi teaches the circuit of claim 11, wherein:
the first current conduction terminal of the eleventh transistor is configured to receive a voltage from a voltage source (Ahmadi, Fig. 11 teaches transistor 504 being located in the upper section tied toward the VDD side); and
the second current conduction terminal of the fourteenth transistor is coupled to ground (Ahmadi, Fig. 11 teaches transistor 514 being located in the upper section tied toward the ground side).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of connecting the transistors to a voltage & ground source.
The suggestion/motivation for doing so would be to enable voltage control within the circuit.
Regarding claim 13, the combination of Chen in view of Ahmadi teaches the circuit of claim 1, wherein: the first and tenth transistors are p-type transistors, the control terminals of the first and tenth transistors are respective gate terminals of the first and tenth transistors, the first current conduction terminals of the first and tenth transistors are respective source terminals of the first and tenth transistors, and the second current conduction terminals of the first and tenth transistors are respective drain terminals of the first and tenth transistors; and the second, ninth and eighth transistors, fourth, fifth, and diode-connected transistors are n-type transistors, the control terminals of the second, fourth, fifth, and sixth transistors are respective gate terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, the first current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistor are respective drain terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, and the second current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors are respective source terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors (Chen, col. 4, lines 47-49, “Each transistor Mp[.] may be a p-channel MOS transistor, and each transistor Mn[.] may be an n-channel MOS transistor”). Chen teaches that the transistors may be implemented as p-channel or n-channel MOS transistors depending on implementation. Selecting the transistor type is a design choice and would have been obvious to a person of ordinary skill in the art.
Regarding claim 14, Chen teaches a circuit (Chen, Fig. 2), comprising:
a first transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal configured to receive a first input (Chen, Fig. 2, transistor Mp[1]);
a second transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the first transistor to form a series connection between the first transistor and the second transistor, the control terminal configured to receive the first input (Chen, Fig. 2, transistor Mp[2]);
a tenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the second transistor, the control terminal configured to receive a second input (Chen, Fig. 2, transistor Mp[3]); and
a ninth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the third transistor to form a series connection between the tenth transistor and the ninth transistor, the control terminal configured to receive a third input (Chen, Fig. 2, transistor Mp[4]).
Chen fails to teach a seventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the tenth transistor, the control terminal configured to receive a fourth input; and a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the first diode-connected transistor to form a diode and the first current conduction terminal of the fifth-seventh transistor.
However, Ahmadi, in an analogous art teaches a seventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the tenth transistor, the control terminal configured to receive a fourth input (Ahmadi, Fig. 6, transistor 506; transistor 506 equates to a seventh transistor and any transistor that is connected to the same node equates to a tenth transistor); and a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the first diode-connected transistor to form a diode and the first current conduction terminal of the fifth-seventh transistor (Ahmadi, Fig. 6, transistor 570; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
Chen and Ahmadi are both considered to be analogous to the claimed invention because both are in the same field of scan flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of a transistor and diode-connected transistor being connected.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Claim 15 is a circuit with limitations similar to the circuit of claim 2, and is rejected under the same rationale.
Regarding claim 16, the combination of Chen in view of Ahmadi teaches the circuit of claim 14, further comprising:
an eighth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the ninth transistor (Chen, Fig. 2, transistor Mn[4]); and
a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the a second diode-connected transistor to form a diode and the first current conduction terminal of the an eighth transistor (Ahmadi, Fig. 6, transistor 572; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of a transistor and diode-connected transistor being connected.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Regarding claim 17, the combination of Chen in view of Ahmadi teaches the circuit of claim 16, wherein: the control terminal of the eighth transistor is configured to receive a scan data input (Ahmadi, Fig. 11 teaches the gate of transistor 506 being a scan input/scan data input [SI]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Chen to incorporate the teachings of Ahmadi by including the functionality of the control terminal of the seventh transistor being configured to receive a scan data input.
The suggestion/motivation for doing so would be to control the signal path of the circuit since transistors are commonly controlled by input signals to control the operation of the circuit.
Claim 18 is a circuit with limitations similar to the circuit of claim 7, and is rejected under the same rationale.
Claim 19 is a circuit with limitations similar to the circuit of claim 10, and is rejected under the same rationale.
Claim 20 is a circuit with limitations similar to the circuit of claim 11, and is rejected under the same rationale.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ahmadi, as applied to claim 1 above, and further in view of Plavec et al. (US 9,535,109), hereinafter Plavec.
Regarding claim 3, the combination of Chen in view of Ahmadi teaches the circuit of claim 2, but fails to teach wherein: the second current conduction terminal of the second diode-connected transistor is coupled to ground.
However, Plavec, in an analogous art, teaches wherein: the second current conduction terminal of the second diode-connected transistor is coupled to ground (Plavec, Abstract, lines 2-9, “The fault detection assembly includes… a second diode connected with one end to the input port and connected with the other end to the ground port… At least one of first and second diodes includes a first diode connected MOS transistor…” [shortened for brevity]).
Chen, Ahmadi, and Plavec are considered to be analogous to the claimed invention because they are in the same field of integrated circuits using transistor circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Chen in view of Ahmadi to incorporate the teachings of Plavec by including the functionality of a diode-connected transistor that is coupled to a ground port.
The suggestion/motivation for doing so would be to provide volage sensing, protection, or voltage drop functionality since diode-connected transistors are commonly used in integrated circuits for these purposes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wong et al. (US 11,366,162) teaches scan flip-flop circuitry with a transistor stack connected serially.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE V BRADEN whose telephone number is (703)756-5381. The examiner can normally be reached Mon-Fri: 9AM-5:30 PM ET.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112