Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 30th, 2026 has been entered. Claims 1-20 are pending in this application. Applicant amended independent claims 1 and 14, as well as dependent claim 13.
Applicant amended independent claims 1 and 14 to further clarify the transistor connections, including amending certain limitations from “coupled” to “connected directly.”
Applicant’s amendments to the claims have been fully considered. The previous rejections set forth in the previously set forth in the previous Office action mailed April 7th, 2026 have been reconsidered in view of the arguments. New grounds of rejection are set forth below based on the amended claim language.
Response to Arguments
Applicant’s arguments, see pgs. 9-12, filed June 30th, 2026, with respect to the rejection(s) of claims 1-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Specifically, Applicant argues that the previously cited references fail to teach the transistor connections taught by the amended claims. The prior art rejections have therefore been reconsidered in view of Applicant’s arguments and the amended claim language.
However, upon further consideration, a new ground(s) of rejection is made in view of Umezaki (US 11,971,638), in view of Ahmadi (US 7,649,395). The newly applied references teach or suggest the transistor arrangements, including the directly connected current-conduction terminals and diode-connected transistor arrangements, as mapped in the rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "a ninth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the third transistor" in lines 14-16. There is insufficient antecedent basis for the “third transistor” limitation in the claim. The claim does not previously teach or introduce a third transistor. Accordingly, it is unclear which transistor is intended by the “third transistor,” rendering the scope of the claim indefinite.
For purposes of examination, the “third transistor” is interpreted as referring to the “tenth transistor,” because the claim subsequently teaches that the connection forms a “series connection between the tenth transistor and the night transistor.”
Claims 15-20 are dependent on claim 14, and are therefore rejected under the same rationale.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-6, 10-12, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Umezaki (US 11,971,638), in view of Ahmadi (US 7,649,395).
Regarding claim 1, Umezaki teaches a circuit (Umezaki, Fig. 19), comprising:
a first transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal configured to receive a first input (Umezaki, Fig. 19, transistor 103);
a second transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal connected directly to the second current conduction terminal of the first transistor to form a series connection between the first transistor and the second transistor, the control terminal configured to receive the first input (Umezaki, Fig. 19, transistor 104; the figure teaches transistor 103 being connected to transistor 104 via wiring 112);
a tenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal directly connected to the first current conduction terminal of the second transistor, the control terminal configured to receive a second input (Umezaki, Fig. 19, transistor 1305; the figure teaches transistor 1305’s corresponding conduction terminal also being connected to wiring 112);
a ninth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the tenth transistor to form a series connection between the tenth transistor and the ninth transistor, the control terminal configured to receive a third input (Umezaki, Fig. 19, transistor 1906; the figure teaches transistor 1906’s corresponding conduction terminal also being connected to wiring 112); and
a eighth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the ninth transistor, the control terminal configured to receive a fourth input (Umezaki, Fig. 19, transistor 1907; the figure teaches transistor 1906 and transistor 1907 having corresponding terminals that meet at node 1922).
Umezaki fails to teach a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the first current conduction terminal of the second diode-connected transistor to form a diode and the second current conduction terminal of the eighth transistor.
However, Ahmadi, in an analogous art, teaches a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the first current conduction terminal of the second diode-connected transistor to form a diode and the second current conduction terminal of the eighth transistor (Ahmadi, Fig. 6, transistor 572; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”; col. 8, lines 14-20, “the additional PMOS diode transistor 570 that is placed in series between transistor 506 and transistor 508… the additional NMOS diode transistor 572 that is placed in series between transistor 520 and transistor 518”).
Umezaki and Ahmadi are both considered to be analogous to the claimed invention because both are in the same field of flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of having a diode-connected transistor in a circuit made up of transistors that form a series connection.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path and to provide propagation delay or internal latency in the scan path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”; col. 8, lines 37-38, “Transistors 572, 570 are thus delay elements which provide a signal propagation delay or internal latency in the scan path”).
Regarding claim 2, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 1, wherein: the first input is a data input (Ahmadi, Fig. 2, data input D 206; col. 4, lines 18-19, “A functional data input 206 is used to provide functional input for normal operation”; Fig. 6 teaches the transistor-level implementation with a first input being a D input); the second input is an inverse scan enable input; the third input is a scan enable input (Ahmadi, Fig. 2, scan enable (SE) input 210; col. 4, lines 20-23, “A scan enable (SE) control input 210 is used to control multiplexer 202 to select either normal mode of operation or scan test mode”; col. 7, lines 17-22, “when the scan enable input is high (SE=1), both transistor 502 and transistor 516 are off. Since transistor 502 is off, there is no signal path between node 581 and node 560. Similarly since transistor 516 is off, there is no signal path 20 between node 590 and node 560. However, when scan enable is high (SE=1) both transistor 508 and transistor 520 are on”; the complementary switching teaches a scan enable and inverse scan enable control arrangement); and the fourth input is a scan data input (Ahmadi, Fig. 2, scan input SI 208, col. 4, lines 19-20, “Scan test data patterns are supplied using the scan input SI 208”; col. 7, lines 17-24 teaches that when the scan enable input equals 1, the output of the multiplexer is determined by SI).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of incorporating data, scan enable, inverse scan enable, and scan data inputs into the circuitry.
The suggestion/motivation for doing so would be to selectively provide either normal data or scan data to the circuit, which allows for the circuit to be able to operate in both normal and scan modes.
Regarding claim 4, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 1, further comprising:
a seventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the tenth transistor (Ahmadi, Fig. 6, transistor 506; transistor 506 equates to a seventh transistor and any transistor that is connected to the same node equates to a tenth transistor); and
a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the a first diode-connected transistor to form a diode and the first current conduction terminal of the seventh transistor (Ahmadi, Fig. 6, transistor 570; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of a transistor and diode-connected transistor being connected.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Regarding claim 5, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 4, wherein: the control terminal of the seventh transistor is configured to receive a scan data input (Ahmadi, Fig. 11 teaches the gate of transistor 506 being a scan input/scan data input [SI]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of the control terminal of the seventh transistor being configured to receive a scan data input.
The suggestion/motivation for doing so would be to control the signal path of the circuit since transistors are commonly controlled by input signals to control the operation of the circuit.
Regarding claim 6, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 5, wherein: the first current conduction terminal of the a first diode-connected transistor is configured to receive a voltage from a voltage source (Ahmadi, Fig. 11 teaches transistor 570 as being located in the upper branch that is connected to VDD).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of a current conduction terminal of a diode-connected transistor being configured to receive a voltage from a voltage source.
The suggestion/motivation for doing so would be to provide a biasing, voltage drop or voltage reference functionality in the circuit.
Regarding claim 10, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 1, further comprising:
an eleventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal (Ahmadi, Fig. 11, transistor 504);
a third transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the eleventh transistor (Ahmadi, Fig. 11, transistor 510);
a fourth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the third transistor (Ahmadi, Fig. 11, transistor 512); and
a fourteenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the fourth transistor, and the control terminal coupled to the control terminal of the eleventh transistor and the second current conduction terminal of the tenth transistor (Ahmadi, Fig. 11, transistor 514).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of the transistor stack taught in Ahmadi.
The suggestion/motivation for doing so would be to control signal propagation, delay or voltage levels within the circuit.
Regarding claim 11, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 10, wherein: the control terminal of the third transistor is configured to receive a clock input (Ahmadi, Fig. 11 teaches an CK gate for transistor 510); and the control terminal of the fourth transistor is configured to receive an inverse clock input (Ahmadi, Fig. 11 teaches an inverse CK gate for transistor 512).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of control terminals of the third and fourth transistors receiving clock and inverse clock signals.
The suggestion/motivation for doing so would be to control switching timing and signal propagation in the circuit.
Regarding claim 12, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 11, wherein:
the first current conduction terminal of the eleventh transistor is configured to receive a voltage from a voltage source (Ahmadi, Fig. 11 teaches transistor 504 being located in the upper section tied toward the VDD side); and
the second current conduction terminal of the fourteenth transistor is coupled to ground (Ahmadi, Fig. 11 teaches transistor 514 being located in the upper section tied toward the ground side).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of connecting the transistors to a voltage & ground source.
The suggestion/motivation for doing so would be to enable voltage control within the circuit.
Regarding claim 14, as best understood based on the 35 U.S.C. 112(b) issue identified above, Umezaki teaches a circuit (Umezaki, Fig. 19), comprising:
a first transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal configured to receive a first input (Umezaki, Fig. 19, transistor 103);
a second transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal connected directly to the second current conduction terminal of the first transistor to form a series connection between the first transistor and the second transistor, the control terminal configured to receive the first input (Umezaki, Fig. 19, transistor 104; the figure teaches transistor 103 being connected to transistor 104 via wiring 112);
a tenth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal directly connected to the first current conduction terminal of the second transistor, the control terminal configured to receive a second input (Umezaki, Fig. 19, transistor 1906; the figure teaches transistor 1906’s corresponding conduction terminal also being connected to wiring 112);
a ninth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the third transistor to form a series connection between the tenth transistor and the ninth transistor, the control terminal configured to receive a third input (Umezaki, Fig. 19, transistor 1305; the figure teaches transistor 1305’s corresponding conduction terminal also being connected to wiring 112); and
a seventh transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the tenth transistor, the control terminal configured to receive a fourth input (Umezaki, Fig. 19, transistor 1907; the figure teaches transistor 1906 and transistor 1907 having corresponding terminals that meet at node 1922).
Umezaki fails to teach a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the first diode-connected transistor to form a diode and the first current conduction terminal of the fifth-seventh transistor.
However, Ahmadi, in an analogous art teaches a first diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the first diode-connected transistor to form a diode and the first current conduction terminal of the fifth-seventh transistor (Ahmadi, Fig. 6, transistor 570; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
Umezaki and Ahmadi are both considered to be analogous to the claimed invention because both are in the same field of flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of having a diode-connected transistor in a circuit made up of transistors that form a series connection.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path and to provide propagation delay or internal latency in the scan path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”; col. 8, lines 37-38, “Transistors 572, 570 are thus delay elements which provide a signal propagation delay or internal latency in the scan path”).
Claim 15 is a circuit with limitations similar to the circuit of claim 2, and is rejected under the same rationale.
Regarding claim 16, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 14, further comprising:
an eighth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the ninth transistor (Umezaki, Fig. 19, transistor 1909; the figure teaches transistor 1305 being connected to transistor 1909 via wiring 112); and
a second diode-connected transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal coupled to the second current conduction terminal of the a second diode-connected transistor to form a diode and the first current conduction terminal of the an eighth transistor (Ahmadi, Fig. 6, transistor 572; col. 8, lines 5-11, “A MOSFET such as transistor 570 or transistor 572 with its gate connected to its drain is referred to as a MOS diode. MOS diodes behave as pn-junction diodes in some respects, as current flows through them in only one direction and there is a voltage differential between their respective source and drain terminals when they are turned on. Thus transistor 570 is a PMOS diode while transistor 572 is an NMOS diode”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of a transistor and diode-connected transistor being connected.
The suggestion/motivation for doing so would be to prevent hold-time violations in a signal path (Ahmadi, col. 6, lines 42-45, “As will become apparent, transistor 570 and transistor 572 provide the required signal propagation delay to prevent hold time violations in the SI signal path”).
Regarding claim 17, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 16, wherein: the control terminal of the eighth transistor is configured to receive a scan data input (Ahmadi, Fig. 11 teaches the gate of transistor 506 being a scan input/scan data input [SI]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Umezaki to incorporate the teachings of Ahmadi by including the functionality of the control terminal of the seventh transistor being configured to receive a scan data input.
The suggestion/motivation for doing so would be to control the signal path of the circuit since transistors are commonly controlled by input signals to control the operation of the circuit.
Claim 19 is a circuit with limitations similar to the circuit of claim 10, and is rejected under the same rationale.
Claim 20 is a circuit with limitations similar to the circuit of claim 11, and is rejected under the same rationale.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Umezaki in view of Ahmadi, as applied to claim 1 above, and further in view of Plavec et al. (US 9,535,109), hereinafter Plavec.
Regarding claim 3, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 2, but fails to teach wherein: the second current conduction terminal of the second diode-connected transistor is coupled to ground.
However, Plavec, in an analogous art, teaches wherein: the second current conduction terminal of the second diode-connected transistor is coupled to ground (Plavec, Abstract, lines 2-9, “The fault detection assembly includes… a second diode connected with one end to the input port and connected with the other end to the ground port… At least one of first and second diodes includes a first diode connected MOS transistor…” [shortened for brevity]).
Umezaki, Ahmadi, and Plavec are considered to be analogous to the claimed invention because they are in the same field of integrated circuits using transistors.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Umezaki in view of Ahmadi to incorporate the teachings of Plavec by including the functionality of a diode-connected transistor that is coupled to a ground port.
The suggestion/motivation for doing so would be to provide voltage sensing, protection, or voltage drop functionality since diode-connected transistors are commonly used in integrated circuits for these purposes.
Claims 7-9, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Umezaki in view of Ahmadi, as applied to claim 1 above, and further in view of Chen et al. (US 9,310,435), hereinafter Chen.
Regarding claim 7, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 1, but fails to teach further comprising:
a fifth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the first transistor; and
a sixth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the second transistor.
However, Chen, in an analogous art teaches a fifth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the second current conduction terminal coupled to the first current conduction terminal of the first transistor; and a sixth transistor having a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal coupled to the second current conduction terminal of the second transistor (Chen, Fig. 2 teaches additional transistors arranged in series with respective transistors of a complementary transistor circuit, including a p-channel transistor [Mp1] having a source coupled to the drain transistor P1 and an n-channel transistor [Mn1] having a source coupled to the drain transistor N1).
Umezaki, Ahmadi, and Chen are considered to be analogous to the claimed invention because they are in the same field of flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Umezaki in view of Ahmadi to incorporate the teachings of Chen by including the functionality of having additional transistors connected in series with respective transistors.
The suggestion/motivation for doing so would be to reduce leakage current through the transistor paths.
Regarding claim 8, the combination of Umezaki in view of Ahmadi, further in view of Chen, teaches the circuit of claim 7, wherein: the control terminal of the fifth transistor is configured to receive a scan enable input (Chen, Fig. 2 teaches an SE gate for transistor P3); and
the control terminal of the sixth transistor is configured to receive an inverse scan enable input (Chen, Fig. 2 teaches an SEB gate for transistor N3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Umezaki in view of Ahmadi to incorporate the teachings of Chen by including the functionality of having control terminals of the additional transistors receive scan enable and inverse scan enable signals.
The suggestion/motivation for doing so would be to selectively control conduction through the transistor paths in response to the scan enable signal.
Regarding claim 9, the combination of Umezaki in view of Ahmadi, further in view of Chen, teaches the circuit of claim 8, wherein:
the first current conduction terminal of the fifth transistor is configured to receive a voltage from a voltage source (Chen, Fig. 2 teaches transistor P3 being connected to Vdd); and
the second current conduction terminal of the sixth transistor is coupled to ground (Chen, Fig. 2 teaches transistor P3 being connected to G).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Umezaki in view of Ahmadi to incorporate the teachings of Chen by including the functionality of configuring the additional transistors to be coupled to a voltage source and ground.
The suggestion/motivation for doing so would be to provide the appropriat3e supply voltages for operation of the circuit.
Regarding claim 13, the combination of Umezaki in view of Ahmadi teaches the circuit of claim 1, but fails to teach wherein: the first and tenth transistors are p-type transistors, the control terminals of the first and tenth transistors are respective gate terminals of the first and tenth transistors, the first current conduction terminals of the first and tenth transistors are respective source terminals of the first and tenth transistors, and the second current conduction terminals of the first and tenth transistors are respective drain terminals of the first and tenth transistors; and the second, ninth and eighth transistors, fourth, fifth, and diode-connected transistors are n-type transistors, the control terminals of the second, fourth, fifth, and sixth transistors are respective gate terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, the first current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistor are respective drain terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, and the second current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors are respective source terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors.
However, Chen, in an analogous art teaches wherein: the first and tenth transistors are p-type transistors, the control terminals of the first and tenth transistors are respective gate terminals of the first and tenth transistors, the first current conduction terminals of the first and tenth transistors are respective source terminals of the first and tenth transistors, and the second current conduction terminals of the first and tenth transistors are respective drain terminals of the first and tenth transistors; and the second, ninth and eighth transistors, fourth, fifth, and diode-connected transistors are n-type transistors, the control terminals of the second, fourth, fifth, and sixth transistors are respective gate terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, the first current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistor are respective drain terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors, and the second current conduction terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors are respective source terminals of the second, ninth and eighth transistors, fourth, fifth, and second diode-connected transistors (Chen, col. 4, lines 47-49, “Each transistor Mp[.] may be a p-channel MOS transistor, and each transistor Mn[.] may be an n-channel MOS transistor”). Chen teaches that the transistors may be implemented as p-channel or n-channel MOS transistors depending on implementation. Selecting the transistor type is a design choice and would have been obvious to a person of ordinary skill in the art.
Umezaki, Ahmadi, and Chen are considered to be analogous to the claimed invention because they are in the same field of flip-flop circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Umezaki in view of Ahmadi to incorporate the teachings of Chen by including the functionality of implementing the transistors of the circuit using P-type and N-type MOS transistors with source and drain terminal arrangements.
The suggestion/motivation for doing so would be to provide complementary transistor operation.
Claim 18 is a circuit with limitations similar to the circuit of claim 7, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Vrudhula et al. (US 10,447,249) teaches transistor circuitry and interconnections between transistor conduction terminals.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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