DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Final.
This action is responsive to the following communication: the response filed on 10-29-2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1, 8, 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
For example, amended claim 1 recites the following:
1. (Currently Amended) One or more processors comprising:
circuitry to scale one or more clocks of one or more cores based, at least in part, on a comparison of a proximity of the one or more cores to each other and one or more patterns of core utilization that indicate a relationship between the proximity and temperature.
MPEP § 2151.01 states, in part that “to satisfy the written description, the specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor has possession of the claimed invention at the time of the filling”.
The highlighted portion directed to claim 1 above was amended by Applicant’s in response to the Non-Final Office Action filed on July 29, 2025. Reviewing the amendment, the Office respectfully submits the specification fails to disclose the invention directed to (i) comparison of a proximity of one or more cores to each other and (ii) comparison one or more patterns that indicate a relationship between the proximity and the temperature as currently claimed. (emphasis added) Stated differently, although ¶ [0075] of the Specification does disclose language directed to comparing processor cores against patterns of processor core utilization that languages in not the same as the expression under (i) and (ii). Indeed, a key word search of Applicant’s specification for these expressions yield no results.
Therefore, in view of above findings and the failure for Applicant under the remarks section to indicate the appropriate paragraphs used in supporting the amended subject matter during the response filed on October 29, 2025, it suggests and appropriate, using In Re Cisco Systems v. Cirrex (Fed. Cir. 2017) to conclude that the specification fails to disclose in sufficient detail to one of ordinary skill in the art that Applicant’s had possession of the subject matter directed to the amended claim because “the vast majority of written description problems arise when the patentee amends or adds claims with limitations not found in the original claim set and using language that does not directly map to specification disclosure” .
Claims 8, 15 are rejected under the same rational already described in claim 1.
Dependent are based on already rejected independent claims and are rejected for their dependency because said claims do not cure the deficiencies presented in the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2024/0289182 (hereinafter, “Clay”) in view of U.S. Publication No. 2025/0044845 (hereinafter, “Francis”).
As per claims 1, 8 and 15, Clay discloses one or more processors comprising:
circuitry (processor circuitry 130) to scale [respective workloads] of one or more cores based, at least in part, on a comparison of a proximity of the one or more cores to each other and ( at least ¶s [0036]-[0037] disclose the invention of scaling “respective workload[s]” bases on whether the respective workloads are executed or stopped. Because of that, the system is further configured to “infer a physical layout of the first processing circuitry based on the obtained temperature measurement data from each processor core of the plurality of processor cores of the first processing circuitry. In some examples, the physical layout comprises a spatial positioning of the processor cores within the first processing circuitry.” ¶ [0038] Lastly, the system is further configured to change the temperature of each executing processor core “by spreading the temperature more evenly across the first processing circuitry a thermal degradation of the first processor circuitry may be reduced which yields a better longevity”; ¶s [0037]-[0042] Lastly, ¶ [0055] states “The correlation between the clustering results of each stressed processor core involves comparing the clustering outputs to see which processor cores consistently appear in similar clusters across different sets of stressed processor cores. A high correlation in clustering patterns indicates that certain processor cores are likely in close physical proximity” )
and one or more pattens of core utilization that indicates a relationship between the proximity and temperature, ( ¶ [0066] states “obtaining 320 temperature measurement data from each processor core of the plurality of processor cores, wherein the temperature measurement data is acquired during the executing the respective workloads by the respective processor core of plurality of processor cores” and “inferring 330 a physical layout of the first processing circuitry based on the obtained temperature measurement”. Stated differently, the different processing workload amounts (i.e, utilization) associated with each core causes the different cores to experience different temperatures. (at least Fig’s 3-5) As of a consequence, physical layout of each core component is determined (at least Fig 6) Further, ¶ [0055] states “The correlation between the clustering results of each stressed processor core involves comparing the clustering outputs to see which processor cores consistently appear in similar clusters across different sets of stressed processor cores. A high correlation in clustering patterns indicates that certain processor cores are likely in close physical proximity” )
Clay does not distinctly disclose circuitry to scale one or more clocks.
However, Francis explicitly discloses the invention directed to circuitry to scale one or more clocks. In particular, Francis discloses the following:
circuitry to scale one or more clocks (¶ [0069] states “voltage and frequency scaling (VFS) may happen largely as a response to execution of high-power consuming instructions to prevent SOCs” ) of one or more cores based, at least in part, on a comparison of a proximity of the one or more cores to each other of the one or more cores to each other and one or more patterns of core utilization that indicate a relationship between the proximity and temperature.( at least ¶ [0092] discloses a system of obtaining “utilization data” and “thermal data” that “prevents thermal runaway based on positional and spatial thermal properties of regions of the SOC 400” that enables the system to apply “tunability” ¶ [0107]) . Alternatively, Fig’s 3 and 8 also illustrates the concept of obtaining utilization data and thermal data that causes the system to receive data that includes information from at least thermal design to be “compared” another component or region in the SOC 400 ¶ [0087] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Clay and Francis because both references are in the same field of endeavor. Francis’s teaching of scaling the frequencies of processing units would enhance Clay's system by allowing the system to optimize performance and power consumption.
As per claims 2, 9, 16, Clay as modified discloses wherein the one or more circuits are to scale the one or more clocks based, at least in part, on one or more patterns of core utilization that are indicative of one or more thermal conditions. (Clay: at least ¶s [0036]-[0037] disclose the invention of scaling “respective workload[s]” bases on whether the respective workloads are executed or stopped. The system is further configured to change the temperature of each executing processor core “by spreading the temperature more evenly across the first processing circuitry a thermal degradation of the first processor circuitry may be reduced which yields a better longevity”; ¶s [0037]-[0042]) & (Francis:¶s [0069], [0092], [0107] and [0087])
As per claims 3, 10, 17, Clay as modified discloses wherein the one or more circuits are to avoid one or more patterns of core utilization that would result in one or more adverse thermal conditions. (Clay: at least ¶s [0036]-[0037] disclose the invention of scaling “respective workload[s]” bases on whether the respective workloads are executed or stopped. The system is further configured to change the temperature of each executing processor core “by spreading the temperature more evenly across the first processing circuitry a thermal degradation of the first processor circuitry may be reduced which yields a better longevity”; ¶s [0037]-[0042]) & (Francis:¶s [0069], [0092], [0107] and [0087]))
As per claims 4, 11, 18, Clay as modified discloses wherein the one or more circuits are to select one or more cores of the processor to perform one or more threads based, at least in part, on avoidance of one or more patterns of core utilization that are indicative of one or more adverse thermal conditions. (Clay: at least ¶s [0036]-[0037] disclose the invention of scaling “respective workload[s]” bases on whether the respective workloads are executed or stopped. The system is further configured to change the temperature of each executing processor core “by spreading the temperature more evenly across the first processing circuitry a thermal degradation of the first processor circuitry may be reduced which yields a better longevity”; ¶s [0037]-[0042]) & (Francis:¶s [0069], , [0092], [0107] and [0087])
As per claims 5, 12, 19, Clay as modified discloses wherein are scale the one or more clocks based on information indicative of one or more patterns of core utilization stored in one or more configuration files. (Francis:¶s [0069], , [0092], [0107] and [0087], files [0175])
As per claims 6, 13, 20, Clay as modified discloses wherein the one or more circuits are to compare utilization of cores of the processor to one or more patterns of core utilization. (Francis:¶s [0069], , [0092], [0107] and [0087], files [0175])) & (Clay: measurement data of the workload executing processor core is below a predetermined threshold.¶ [0037], The correlation between the clustering results of each stressed processor core involves comparing the clustering outputs to see which processor cores consistently appear in similar clusters across different sets of stressed processor cores. ¶ [0055])
As per claims 7, and 14 Clay as modified discloses a processors wherein proximity of the one or more cores corresponds to one or more locations of the one or more cores on a chip of the processor. (Clay: Fig’s 3A-B, Fig 7) & (Francis:¶s [0069], , [0092], [0107] and [0087], files [0175])
Relevant Prior Art
Pertinent prior art for the instant application is U.S. Patent No. 9,256,276 which discloses a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage (abstract)
Response to Arguments
Applicant's arguments filed on October 29, 2025 are directed to the newly added features which have address by the rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov