DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/21/2026.
Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on 7/21/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Note: Fig. 11, a second gate dielectric layer 158 is deposited to cover the exposed semiconductor layers 124 in the logic device regions, however first gate dielectric layer 150 is already removed from logic device nanosheet channel.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 1; line 6 and claim 8; line 8, claimed that “a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel”. However [0054] recited that a second gate dielectric layer 158 is deposited to cover the exposed semiconductor layers 124 in the logic device regions- because the first gate dielectric layer 150 is already removed from logic device region. Therefore “a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel” is not disclosed in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bao, US 2023/0187496, in view of Cheng, US 2019/0157420 and further in view of Lin, US 2024/0038872.
Regarding claims 1, 2 and 3, Bao discloses in claim 1; a semiconductor device, comprising: an input/output device (Fig. 1-12 and [0028]; I/O device 100B) having a constructed fin channel extending orthogonally relative to a plane of a substrate (Fig. 1-12 and [0027, 0029]; nanosheet fin 210 with semiconductor channel 110 extending orthogonally relative to the top surface of substrate 102); a first gate dielectric layer (Fig. 12 and [0064]; high-k dielectric 912) disposed on the portions; a logic device having a nanosheet channel (Fig. 1-12 and [0028]; logic device 100A with nanosheet stack of channel layers 110). Bao substantially discloses the invention of an integrated circuit having a logic device and an I/O device with nanosheet stacks of gate-all-around transistors but silent about the constructed fin channel including faceted portions in claim 1, the faceted portions include periodic faceted surfaces having a periodicity in accordance with nanosheets in claim 2 and the faceted portions include a diamond-like shape in claim 3. However, Cheng teaches that nanosheet transistor with nanosheet channel layers stacks with periodic diamond like faceted portions (Fig. 5-13 and [0037]; 21). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Bao by providing the constructed fin channel including faceted portions in claim 1, the faceted portions include periodic faceted surfaces having a periodicity in accordance with nanosheets in claim 2 and the faceted portions include a diamond-like shape in claim 3, so that techniques and structures as disclosed can provide substantial beneficial technical effects. By way of example only and without limitation, one or more embodiments may provide one or more of the following advantages: to provide one or more of the following advantages: Spacer formation without conventional spacer RIE or timed etch; Improved junction uniformity; Outer spacer, inner spacer and ILD liner can be formed of the same material; Allows concurrent outer spacer and ILD liner formation ([0009-0012]). Bao, in view of Cheng substantially discloses the invention of an integrated circuit having a logic device and an I/O device with nanosheet stacks of gate-all-around transistors with high-k dielectric is formed surrounding the semiconductor channel layers but silent about a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel. However, Lin teaches that gate dielectric 182 has a multilayer structure, such as a high-k dielectric layer disposed over an interfacial layer (Fig. 8A-8C and [0054]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Bao, in view of Cheng by providing a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel, so that to improve device performance, replacing polysilicon gate electrodes with metal gate electrodes, to provide devices having different threshold (operating) voltages [0003].
Regarding claim 4, Bao discloses; the constructed fin channel includes inner spacers embedded therein (Fig. 12; remaining semiconductor layers 108 act as spacers for nanosheet fin channel layers 110 at I/O device 100B).
Regarding claim 7, Bao discloses; the constructed fin channel includes nanosheets joined by epitaxial semiconductor material (Fig. 1-12 and [ 0055]; semiconductor channel layers 110, i.e., using an epitaxial growth process).
Regarding claims 8, 9 and 10, Bao discloses in claim 8; a semiconductor device, comprising: an input/output device (Fig. 1-12 and [0028]; I/O device 100B) having a constructed fin channel extending orthogonally relative to a plane of a substrate (Fig. 1-12 and [0027, 0029]; nanosheet fin 210 with semiconductor channel 110 extending orthogonally relative to the top surface of substrate 102); a first gate dielectric layer (Fig. 8-11 and [0028]; oxide layer 820) disposed on the portions; a logic device having a nanosheet channel (Fig. 1-12 and [0028]; logic device 100A with nanosheet stack of channel layers 110); and a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel (Fig. 12 and [0065]; dielectric 912 disposed on the oxide layer 820). Bao substantially discloses the invention of an integrated circuit having a logic device and an I/O device with nanosheet stacks of gate-all-around transistors but silent about the constructed fin channel including faceted portions with peaks and valleys on an outer surface of the constructed fin channel in claim 8, the faceted portions include periodic faceted surfaces having a periodicity in accordance with nanosheets in claim 9 and the faceted portions include a diamond-like shape in claim 10. However, Cheng teaches that nanosheet transistor with nanosheet channel layers stacks with periodic diamond like faceted portions (Fig. 5-13 and [0037]; 21). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Bao by providing the constructed fin channel including faceted portions with peaks and valleys on an outer surface of the constructed fin channel in claim 8, the faceted portions include periodic faceted surfaces having a periodicity in accordance with nanosheets in claim 9 and the faceted portions include a diamond-like shape in claim 10, so that techniques and structures as disclosed can provide substantial beneficial technical effects. By way of example only and without limitation, one or more embodiments may provide one or more of the following advantages: to provide one or more of the following advantages: Spacer formation without conventional spacer RIE or timed etch; Improved junction uniformity; Outer spacer, inner spacer and ILD liner can be formed of the same material; Allows concurrent outer spacer and ILD liner formation ([0009-0012]). Bao, in view of Cheng substantially discloses the invention of an integrated circuit having a logic device and an I/O device with nanosheet stacks of gate-all-around transistors with high-k dielectric is formed surrounding the semiconductor channel layers but silent about a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel. However, Lin teaches that gate dielectric 182 has a multilayer structure, such as a high-k dielectric layer disposed over an interfacial layer (Fig. 8A-8C and [0054]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Bao, in view of Cheng by providing a second gate dielectric layer disposed on the first gate dielectric layer on the nanosheet channel, so that to improve device performance, replacing polysilicon gate electrodes with metal gate electrodes, to provide devices having different threshold (operating) voltages [0003].
Regarding claim 11, Bao discloses; the constructed fin channel includes inner spacers embedded therein (Fig. 12; remaining semiconductor layers 108 act as spacers for nanosheet fin channel layers 110 at I/O device 100B).
Regarding claim 14, Bao discloses; the constructed fin channel includes nanosheets joined by epitaxial semiconductor material (Fig. 1-12 and [ 0055]; semiconductor channel layers 110, i.e., using an epitaxial growth process).
Claim(s) 5-6 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Bao, US 2023/0187496, in view of Cheng, US 2019/0157420 and further in view of Lin, US 2024/0038872, as applied to claims 1-4, 7-11 and 14 above, and further in view of official notice with evidence provided by IEEE Technology navigator, [retrieved on 2026-09-29], Retrieved from Internet: High-k gate dielectrics | IEEE Technology Navigator.
Regarding claims 5-6 and 12-13, Bao discloses; a gap between nanosheets in the nanosheet channel (Fig. 1-12 and [0050, 0055]; semiconductor layers 108 and the semiconductor channel layers 110, i.e., thickness varying from approximately 1 nm to approximately 10 nm, therefore the gap between channel layers 110 after removing layers 108 is approximately 1 nm to approximately 10 nm). whereas Bao also discloses that the high-k dielectric 912 includes a layer of silicon oxide and a layer of a high-k dielectric material, such as a hafnium based material [0065]. Though Bao in view of Cheng and Lin do not specifically disclose the thickness of high-k dielectric 912, however IEEE Technology navigator teaches that high-k film, a hafnium dioxide (HfO2) layer 3 nm thick. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Bao in view of Cheng and Lin by proving the thickness of the first gate dielectric layer is greater than 3 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation- MPEP 2144.05.II.A.
Conclusion
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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