DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-11, 13-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeon(USPGPUB DOCUMENT: 2022/0139999, hereinafter Yeon) in view of Hwang (USPGPUB DOCUMENT: 2022/0013400, hereinafter Hwang) and Cha (USPGPUB DOCUMENT: 2016/0125804, hereinafter Cha).
Re claim 1 Yeon discloses a display device comprising: a display substrate(substrate of 200/100) comprising a driving circuit[0036]; an array layer(left/right150) provided on the display substrate(substrate of 200/100) and comprising a plurality of grooves(grooves between the left/right 150); a semiconductor chip(SL1/SL2) provided in a groove of the plurality of grooves(grooves between the left/right 150), the semiconductor chip(SL1/SL2) comprising: an n-type semiconductor layer(142/147/122/127); an active layer(145/125) provided on the n-type semiconductor layer(142/147/122/127); a p-type semiconductor layer(142/147/122/127) provided on the active layer(145/125); and a first electrode(165A/165B) provided on the p-type semiconductor layer(142/147/122/127); a first wiring[0044] connected to the first electrode(165A/165B); and a second wiring[0044] connected to the second electrode(165A/165B).
Yeon does not discloses micro-semiconductor; and a second electrode(165A/165B) connected to the n-type semiconductor layer(142/147/122/127) from a lower surface of the display substrate(substrate of 200/100);a first wiring above the array layer, the first wiring connected to the first electrode;
Hwang discloses micro-semiconductor(130)[0086 of Hwang]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hwang to the teachings of Yeon in order to provide benefits associated with low power consumption and environment-friendly characteristics [0003, Yeon].
Yeon and Hwang does not discloses a second electrode(165A/165B) connected to the n-type semiconductor layer(142/147/122/127) from a lower surface of the display substrate(substrate of 200/100);a first wiring above the array layer, the first wiring connected to the first electrode;
Cha discloses a second electrode(125 of Cha) connected to the n-type semiconductor layer(141/151/161 of Cha) from a lower surface of the display substrate(120/110 of Cha);a first wiring(wire)[0084 of Cha]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cha to the teachings of Yeon in order to allow more natural colors of light to be emitted thereby by associating pixels and light-emitting devices in one-to-one correspondence [0005, Cha]. In doing so, a second electrode(125 of Cha) connected to the n-type semiconductor layer(141/151/161 of Cha) from a lower surface of the display substrate(120/110 of Cha);a first wiring(wire)[0084 of Cha] above the array layer(left/right150), the first wiring(wire)[0084 of Cha] connected to the first electrode(165A/165B);
Re claim 3 Yeon and Hwang and Cha disclose the display device of claim 1, wherein the display substrate(substrate of 200/100) further comprises a via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) through which the micro-semiconductor chip(SL1/SL2) is exposed, and the second electrode(165A/165B) is provided in the via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole).
Re claim 4 Yeon and Hwang and Cha disclose the display device of claim 1, further comprising a reflective layer provided on a sidewall of each of the plurality of grooves(grooves between the left/right 150).
Re claim 5 Yeon and Hwang and Cha disclose the display device of claim 1, wherein the first wiring[0044] faces away from the second electrode(165A/165B).
Re claim 6 Yeon and Hwang and Cha disclose the display device of claim 1, wherein the first wiring[0044] is configured to not contact the second electrode(165A/165B) in a case where the micro-semiconductor chip(SL1/SL2) is omitted from one of the plurality of grooves(grooves between the left/right 150).
Re claim 7 Yeon and Hwang and Cha disclose the display device of claim 1, wherein, in a plan view, the first wiring[0044] has a shape comprising a concave portion and the second electrode(165A/165B) is provided in the concave portion.
Re claim 8 Yeon and Hwang and Cha disclose the display device of claim 1, wherein the first wiring[0044] and the second electrode(165A/165B) are positioned in parallel in a plan view.
Re claim 9 Yeon and Hwang and Cha disclose the display device of claim 1, further comprising an insulating layer is on the array layer(left/right150), wherein a maximum thickness of the insulating layer is greater than a thickness of the array layer(left/right150).
Re claim 10 Yeon and Hwang and Cha disclose the display device of claim 1, further comprising a color conversion layer provided on the array layer(left/right150) and configured to convert a color of light emitted from the micro-semiconductor chip(SL1/SL2).
Re claim 11 Yeon discloses a method of manufacturing a display device that comprises a semiconductor chip(SL1/SL2) comprising an n-type semiconductor layer(142/147/122/127), an active layer(145/125) provided on the n-type semiconductor layer(142/147/122/127), a p-type semiconductor layer(142/147/122/127) provided on the active layer(145/125), and a first electrode(165A/165B) provided on the p-type semiconductor layer(142/147/122/127), the method comprising: forming an array layer(left/right150) on a display substrate(substrate of 200/100) that comprises a driving circuit[0036]; forming a plurality of grooves(grooves between the left/right 150) in the array layer(left/right150); and connecting a first wiring[0044] to the first electrode(165A/165B) and connecting a second wiring[0044] to the second electrode(165A/165B).
Yeon does not discloses micro-semiconductor; transferring the semiconductor chip(SL1/SL2) to one of the plurality of grooves(grooves between the left/right 150) so that the first electrode(165A/165B) is positioned in an upper portion of the one of the plurality of grooves(grooves between the left/right 150); exposing the n-type semiconductor layer(142/147/122/127) of the micro-semiconductor chip(SL1/SL2) by forming a via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) in the display substrate(substrate of 200/100) from a lower surface of the display substrate(substrate of 200/100); forming a second electrode(165A/165B) in the via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) and connecting the second electrode(165A/165B) to the n-type semiconductor layer(142/147/122/127); forming an array layer on a display substrate, the display substrate comprising a driving circuit; and connecting a first wiring to the first electrode and connecting a second wiring to the second electrode, the first wiring being above the array layer
Hwang discloses micro-semiconductor(130)[0086 of Hwang]; transferring[0088-0090 of Hwang] the micro-semiconductor chip to one of the plurality of grooves
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hwang to the teachings of Yeon in order to provide benefits associated with low power consumption and environment-friendly characteristics [0003, Yeon]. In doing so, transferring[0088-0090 of Hwang] the micro-semiconductor chip(130)[0086 of Hwang] to one of the plurality of grooves(grooves between the left/right 150) so that the first electrode(165A/165B) is positioned in an upper portion of the one of the plurality of grooves(grooves between the left/right 150);
Yeon and Hwang does not discloses exposing the n-type semiconductor layer(142/147/122/127) of the micro-semiconductor chip(SL1/SL2) by forming a via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) in the display substrate(substrate of 200/100) from a lower surface of the display substrate(substrate of 200/100); forming a second electrode(165A/165B) in the via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) and connecting the second electrode(165A/165B) to the n-type semiconductor layer(142/147/122/127); forming an array layer on a display substrate, the display substrate comprising a driving circuit; and connecting a first wiring to the first electrode and connecting a second wiring to the second electrode, the first wiring being above the array layer
Cha discloses exposing the n-type semiconductor layer(141/151/161 of Cha) of the micro-semiconductor chip(140/150/160 of Cha) in the display substrate(120/110 of Cha) from a lower surface of the display substrate(120/110 of Cha); forming a second electrode(125 of Cha) and connecting the second electrode(125 of Cha) to the n-type semiconductor layer(141/151/161 of Cha); the display substrate(120/110 of Cha) comprising a driving circuit(30 of Cha); and connecting a second wiring(wire)[0084 of Cha]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cha to the teachings of Yeon in order to allow more natural colors of light to be emitted thereby by associating pixels and light-emitting devices in one-to-one correspondence [0005, Cha]. In doing so, exposing the n-type semiconductor layer(141/151/161 of Cha) of the micro-semiconductor chip(140/150/160 of Cha) by forming a via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) in the display substrate(120/110 of Cha) from a lower surface of the display substrate(120/110 of Cha); forming a second electrode(125 of Cha) in the via hole(since there are recesses or grooves between left/right 159, this may be interpreted as a via hole) and connecting the second electrode(125 of Cha) to the n-type semiconductor layer(141/151/161 of Cha); forming an array layer(left/right150) on a display substrate(120/110 of Cha), the display substrate(120/110 of Cha) comprising a driving circuit(30 of Cha); and connecting a first wiring(wire)[0084 of Cha] to the first electrode(165A/165B) and connecting a second wiring(wire)[0084 of Cha] to the second electrode(165A/165B), the first wiring being above the array layer(left/right150)
Re claim 13 Yeon and Hwang and Cha disclose the method of claim 11, wherein the micro-semiconductor chip(SL1/SL2) is transferred by using a wet self-alignment method.
Re claim 14 Yeon and Hwang and Cha disclose the method of claim 11, further comprising forming a reflective layer on a sidewall of each of the plurality of grooves(grooves between the left/right 150).
Re claim 15 Yeon and Hwang and Cha disclose the method of claim 11, wherein the first wiring[0044] does not overlap with the second electrode(165A/165B).
Re claim 16 Yeon and Hwang and Cha disclose the method of claim 11, wherein the first wiring[0044] is configured not to contact the second electrode(165A/165B) in a case where the micro-semiconductor chip(SL1/SL2) is omitted from the one of the plurality of grooves(grooves between the left/right 150).
Re claim 17 Yeon and Hwang and Cha disclose the method of claim 11, wherein, in a plan view, the first wiring[0044] has a shape including a concave portion and the second electrode(165A/165B) is in the concave portion.
Re claim 18 Yeon and Hwang and Cha disclose the method of claim 11, wherein the first wiring[0044] and the second electrode(165A/165B) are positioned in parallel in a plan view.
Re claim 19 Yeon and Hwang and Cha disclose the method of claim 11, further comprising forming an insulating layer is on the array layer(left/right150), wherein a maximum thickness of the insulating layer is greater than a thickness of the array layer(left/right150).
Re claim 20 Yeon and Hwang and Cha disclose the method of claim 11, further comprising forming a color conversion layer on the array layer(left/right150), the color conversion layer being configured to convert a color of light emitted from the micro-semiconductor chip(SL1/SL2).
Re claim 21 Yeon and Hwang and Cha disclose the display device of claim 1,
Yeon and Hwang and Cha do not disclose the display device of claim 1, wherein the plurality of grooves (grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip
Although the combination of Yeon and Hwang and Cha do not disclose the display device of claim 1, wherein the plurality of grooves (grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose the display device of claim 1, wherein the plurality of grooves (grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the natural colors of light [0005, Cha] characteristics. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 22 Yeon and Hwang and Cha disclose the method of claim 11,
Yeon and Hwang and Cha do not disclose wherein the plurality of grooves(grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip
Although the combination of Yeon and Hwang and Cha do not disclose wherein the plurality of grooves(grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein the plurality of grooves(grooves between the left/right 150) have a depth less than a maximum thickness of the micro-semiconductor chip as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the natural colors of light [0005, Cha] characteristics. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-11, 13-22 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
