DETAILED ACTION
This action is responsive to the application No. 18/597,807 filed on March 6, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III, corresponding to claims 1-25, in the reply filed on July 7, 2026, is acknowledged.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, all dies rotated by 0 (or 180) degrees, the routing layer, the controlled collapse chip connection signals, and the controlled collapse chip connection signals escaped on the same routing layer, must be shown or the feature(s) canceled from the claim(s). Also, the claimed all dies rotated by 90 degrees is not shown in the elected species. Fig. 4 only shows two dies “rotated” by 0 degrees with respect to two other dies that are rotated by 180 degrees from the first two dies, while no dies are rotated by 90 degrees, as best understood. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites identical integrated circuits are rotated by either 0 degrees, 90 degrees, or 180 degrees. This limitation encompasses all dies not rotated (all at 0 degrees), or all dies rotated 90 degrees, or all dies rotated 180 degrees. None of these alternatives are shown in the elected species (Fig. 4). There is no written description or corresponding figures supporting all dies rotated 0 degrees, or all dies rotated 180 degrees, and with respect to the elected species (Fig. 4), no dies are rotated 90 degrees, commensurate in scope with claim 1.
Claim 18 similarly recites two identical integrated circuits are rotated by 0 degrees or 180 degrees with respect to two other identical integrated circuits. This limitation encompasses all dies not rotated (all 0 degrees) or all dies rotated 180 degrees. None of these arrangements encompassed by the claim language have written description support and are not shown in the elected species (Fig. 4). There is no written description or corresponding figures supporting all dies rotated 0 degrees, or all dies rotated 180 degrees commensurate in scope with claim 18.
To the extent claims 1 and 18 are construed to encompass all arrangements falling within the rotation claim language including independent 0, 90, and 180 degree rotation selections, all at 0 and all at 180 arrangements, this would result in different pair groupings, different die-edge connections, and different macro orientations. The original disclosure does not demonstrate possession of, or provide written description support for the entirety of the claimed genus. The elected Fig. 4 species does not depict a 90 degree rotated die and does not establish a general principle showing that arbitrary undisclosed rotations and die arrangements preserve the asserted pinwheel routing or stated routing-layer benefit. Also, with respect to the claimed rotations, a die may be rotated by 180 degrees to flip the die upside-down, however this is not disclosed or contemplated by Applicant.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 18 recite “integrated circuits” and claims 15 and 19 recite “integrated circuits are shaped in a rectangular manner”. It appears Applicant is conflating an integrated circuit with a die or chip. None of the drawings show the actual integrated circuits, understood to be the semiconductor device circuits formed in or on a semiconductor substrate comprising transistors, interconnects, etc. The drawings clearly depict the “dies” or “chips”, dies/chips comprise integrated circuits. The dies/chips appearing to be rectangular, not the integrated circuits themselves (details of the actual integrated circuits are not shown in any figure). It is confusing if Applicant actually intends to describe the shape of the integrated circuits which are made up of semiconductor devices and interconnects, etc., e.g. a rectangular gate or a rectangular fin, or the like, or perhaps a rectangular repeating array of transistors, or perhaps a rectangular memory cell layout, still none of these correspond to the shape of the die and none of these details are shown. If Applicant intended to describe identical dies or chips, wherein the dies or chips are rectangular, then it is suggested Applicant use the term die or chip rather than integrated circuit to avoid confusion.
Claim 1 recites identical integrated circuits arranged in a coplanar manner, wherein said identical integrated circuits are rotated by either 0 degrees, 90 degrees or 180 degrees with respect to each other. This limitation is indefinite because it is not clear how many integrated circuits must be rotated with respect to how many other integrated circuits. The “integrated circuits” introduced in line 2 is an unknown quantity, which “are rotated”, understood to mean all of them, while the “with respect to each other”, implies a 1:1 paring. If all of the integrated circuits are rotated, then what is left (non-rotated) to be rotated with respect to? It is not clear if this requires an even number of integrated circuits for pair-wise rotations wherein only half of the integrated circuits are supposed to be rotated in order to leave the other half not rotated to achieve a subset of integrated circuits rotated with respect to each other.
Claim 1 does not identify the rotation axis, reference orientation, angular measurement direction, die pair(s) to be compared, or whether the condition applies pairwise, collectively, or only to neighboring/diagonal integrated circuits. The limitation further does not establish a four-die array or other geometry sufficient to identify “diagonally positioned” integrated circuits.
Claims 1 and 21 recite “pinwheel-shaped connections”, rendering the claims indefinite since there is no standard for “pinwheel-shaped connections”. One would need to guess what is or is not a pinwheel shape. It is also not clear if the intended “pinwheel-shaped connections” refer to all of the connections as a whole, or a single connection, or a pair of connections, etc. Searching the internet for “pinwheel shape”, returns many different shapes, none of which look like Applicant’s pinwheel-shaped connections 105:
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Applicant recites (¶93) “Pinwheel-shaped connections, as used herein, refer to arc-shaped connections in the form of a pinwheel, such as similar to the lightweight vanes that revolve at the end of the stick of the pinwheel.” This description of a children’s toy does not accurately describe 105 in Fig. 4. The requirements of the pinwheel shaped connections are not clear and determining whether or not something is pinwheel shaped is highly subjective. One would not know when infringement occurs. From the first image below (left side), it is not clear which arc(s) of the 3D curved surfaces corresponds to 105.
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Claim 18 is indefinite because “two identical integrated circuits … are rotated by 0 degrees or 180 degrees with respect to two other identical integrated circuits” fails to identify the two-member groups, whether four chips are actually required, the pairwise mapping between groups, whether both groups have internally common orientations, and whether one or both stated angular alternatives must occur. The claim reads on materially different: all 0, all 180, and mixed-orientation arrangements.
Claims 3 and 18 recite “input/output macros”, rendering the claims indefinite since it is unclear what structures are required or excluded by the claimed “input/output macros”. According to the specification, ¶93: “A macro, as used herein, is a reusable piece of logic block that can be used in a design without the necessity of building them from scratch.” This definition does not clarify what structure is required in a “macro”. Applicant defines a macro by it being reused rather than by any particular structure(s) or material(s). It is unclear what a “piece of logic block” is. The claims do not identify the physical structure of a macro, making it unclear when infringement occurs. It is not clear how to compare the claimed “macro” to prior art simply having an I/O terminal, or pins/bumps, or bond pads, or some other electrical connections. The “macros” in Fig. 4 appear to depict rectangular bond pads, and for any semiconductor device, a set of lithography masks will be fabricated, some comprising pads and interconnects, and the lithography masks get reused many times. It is not clear if this results in a “macro” since one is not redesigning the masks for the pad layouts from scratch every time they are reused. Claims 3 and 18 are product claims, while the recited “macros” appear to be drawn to the manner in which parts of an integrated circuit are designed with reused parts from some other design. The metes and bounds are unclear. One would not know when infringement occurs since one cannot determine whether an existing structure (e.g. consider a transistor on a die) was a “macro” (understood to be reused from some prior design) or if a structure (e.g. an identical looking transistor) was made from “scratch” and not reused from a prior design. The structural requirements of the claimed “macros” are not clear. A semiconductor device is distinguishable based on its structure and materials, not based on whether or not it was reused or recycled from a prior design. Next, the recited “asymmetrically placed along edges” is confusing because there is no baseline with respect to how these are asymmetrical (e.g. with respect to a centerline of an individual die, a vertical/horizontal die axis, the perimeter of a die, package/module center, the arrangement of I/O macros on another die, an opposing edge of the same die, etc.). It also does not identify whether the asymmetry must exist on every die, on every edge, for every macro, for a subset, or only globally across the package/module. A configuration could be asymmetric on one edge of one die but entirely symmetric as a module, another could be globally asymmetric but have symmetric patterns on every individual die. Both read on the claims.
Claims 4 and 23 recite input/output macros are spaced to “open a wiring channel” between transmitter macros and receiver macros of said input/output macros. This limitation is unclear as to the requirements for macro spacing “to open a wiring channel”. It is unclear what Fig. 2 is supposed to represent or if it is some abstract depiction of Applicant’s wiring and/or pins having a opening somewhere. Fig. 2 shows an array of 12 rectangles and does not represent any known semiconductor structure, pins, wiring, or an opening. It is entirely unclear how one is to compare the “structure” of Fig. 2 to any prior art wiring or interconnects or dies having pins (noting there are no pins shown in Figs. 2 or 4), or openings. It is also not clear when features are spaced “to open a wiring channel” of unknown dimensions. It is not clear what physical feature is “opened” or if this requires an empty space. It not clear what actual structure is required by “a wiring channel” or how much space a wiring channel requires for it to be opened.
Claim 5 recites “neighboring integrated circuit” without defining neighboring. In a 2x2 die array (noting no claims even define a 2x2 die array), a given die may have two side-neighbors and one diagonal neighbor. In a larger array it can have several. Nothing identifies which one is “neighboring,” which edges face, or whether the claimed transmit/receive pair mapping applies to every pair or just one.
Claim 6 recites “a diagonally located integrated circuit,” however the independent claim does not require the geometry necessary to identify a diagonal counterpart. The phrase only becomes meaningful after defining a 2x2 die array, such as the four-die arrangement shown in Fig. 4.
Claim 9 recites “…transmitter macros and receiver macros of said input/output macro located along each edge of said identical integrated circuits have N rows of controlled collapse chip connection signals, wherein M rows of said controlled collapse chip connection signals are escaped on a same routing layer”. The recited “controlled collapse chip connection signals” is technically and grammatically incoherent as this appears to conflate a physical interconnect structure with an electrical signal. The recited “controlled collapse chip connection signals are escaped on a same routing layer” is also technically and grammatically incoherent. It is not clear what these limitations mean. It is not clear what structure this corresponds to. It is not clear how signals can be arranged in rows or what real structure this actually corresponds to. In addition, “escaped on a same routing layer” is confusing and appears to be grammatically improper. It is unclear what “escaped” means in this context. It is also unclear what “a same routing layer” means, in particular in light of the recited M rows of said controlled collapse chip connection signals. This could be construed as: every one of the M rows is routed entirely on one common layer, each row is routed on its own “same” layer, M rows share at least part of a layer, M rows “escape” on the same layer only near a bump or pin and may move to other layers later, and whether the layer is counted locally beneath each die or globally for the package. Claim 11 similarly recites “controlled collapse chip connection signals” and “controlled collapse chip connection signals are escaped on a same routing layer” and is indefinite for the same reasons discussed above regarding claim 9.
Claim 10 recites N/M wiring layers are used. A physical wiring layer is normally understood to be an integer, e.g. 1, however N/M need not be an integer since the claim provides no constraints on M or N. Furthermore, M could be zero, producing an undefined ratio. M could be greater than N, producing a fractional layer.
Claim 14 recites wiring channels, lacking antecedence.
Claim 17 recites “said integrated circuits correspond to central processors”. This limitation is not clear because the manner in which the integrated circuits must “correspond to” central processors is not clear. This limitation is ambiguous and can be interpreted numerous ways, e.g. the integrated circuits “correspond to” by communicating with the central processors, the integrated circuits “correspond to” by being placed/mounted upon central processors, the integrated circuits are central processors, etc. Applicant’s intent is not clear and it is not clear when infringement occurs.
Claim 18 recites “input/output macros asymmetrically placed along a horizontal center axis and a vertical center axis”, rendering the claim indefinite since these have no disposition or context with respect to the other claimed elements. A horizontal center axis and a vertical center axis of what exactly? These could be a vertical center axis of a single die, or of the entire multi-chip module, or of the center of a macro, etc. A physical package can be rotated 90 degrees in the plane without changing its structure. Without a structural reference the terms “horizontal” and “vertical” are arbitrary. “Along” is also ambiguous as a macro can be: centered on an axis, located with an edge touching/crossing an axis, offset but extending generally parallel to an axis, positioned in a region adjacent to the axis, or located on a die edge that lies along an axis. The claim recites the macros are “asymmetrically placed along” both axes, but does not identify the symmetric condition that is supposedly absent, or any reference frame for determining asymmetry.
Claim 20 recites the integrated circuits have an aspect ratio that is not equal to 1. It is not clear what part of the integrated circuit must have the claimed aspect ratio. An aspect ratio of an integrated circuit could be ascribed to an aspect ratio of a trench, a fin of a finfet, an aspect ratio of a rectangular integrated circuit layout, e.g. a standard cell layout, etc. All physical parts of semiconductor devices have aspect ratios, aspect ratios of “integrated circuits” could be ascribed to anything, it is unclear what claim 20 is referring to.
Claim 24 recites a number of said identical integrated circuits corresponds to four identical integrated circuits. This limitation is indefinite since it is not clear how a number corresponds to four identical integrated circuits. “Corresponds to” implies some relationship but does not define what the relationship is, e.g. a 1:1 correspondence or a 1:4 or 4:1 or some other ratio?
Claim 25 recites wherein said four identical integrated circuits comprise a plurality of input/output macros that are unused, wherein said plurality of unused input/output macros are placed along an outer edge of said four identical integrated circuits. Claim 25 describes how the device is used or operated. It is not clear what structure is required based on whether (or when) parts of the device are used or not used. When a device is powered off, none of the parts are being used. During operation, parts of the device may be unused, at least momentarily, and subsequently used again. The requirements of not using parts of the device are unclear.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 22 and 24 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 22 recites “…a subset of said input/output macros are located on an identical position on said identical integrated circuits with respect to a chip center axis. …”. This limitation does not appear to further limit claim 18 because claim 18 already recites identical integrated circuits, understood to mean identical dies/chips. If each die is identical, then each die will have the same input/output macros in the same locations. The term “identical” means being exactly the same. If the integrated circuits are identical, then claim 22 does not further limit claim 18.
Claim 24 recites a number of said identical integrated circuits corresponds to four identical integrated circuits. Claim 18 already recites four identical integrated circuits: “…two identical integrated circuits of said identical integrated circuits are rotated by 0 degrees or 180 degrees with respect to two other identical integrated circuits of said identical integrated circuits…”, noting 2+2=4. Therefore, claim 24 does not further limit claim 18.
Determining the scope and content of claims 1-25 is not reasonably feasible as substantial guesswork would be involved (see In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962); Ex parte Brummer, 12 USPQ 2d, 1653, 1655 (BdPatApp&Int 1989); and also In re Wilson, 424 F.2d 1382, 165 USPQ 494 (CCPA 1970). In an effort to advance prosecution, prior art pertinent to the disclosed invention is nevertheless cited and Applicant is reminded they must consider all cited art under Rule 111(c) when amending the claims. The Examiner directs Applicant’s attention to at least the following highly pertinent art:
Kwon et al. (US 2017/0125393), see entire disclosure
Hossain et al. (US 2019/0131268), see entire disclosure
Meyer-Berg (US 2006/0060954), see Fig. 2 and corresponding text
Bailey et al. (US 6,735,651), see Fig. 1 and corresponding text
Tanaka (US 2020/0185328), see entire disclosure
Bout et al. (US 2022/0223529), see entire disclosure
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related die arrangements, rotations, and connections between dies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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