DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2-3 and 12 -13 are objected to because of the following informalities:
Claim 2 (claim 12) recites “the BL and SL comprises” which should be replaced with “the BL and SL comprise”.
Claim 3 (claim 13) recites “the BL and SL comprises” which should be replaced with “the BL and SL comprise”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 (claim 18) recites “charge-trapping layers selected from a set comprising oxide-nitride-oxide (ONO) layers, oxide-nitride-oxide-nitride-oxide (ONONO) layers, and oxide-nitride (ON) layers” that requires a material selected from an open list of alternatives, and thus it is unclear what other alternatives are intended to be encompassed by the claim.
Note that Markush grouping is a closed group of alternatives, i.e., the selection is made from a group "consisting of" (rather than "comprising" or "including") the alternative members. Abbott Labs., 334 F.3d at 1280, 67 USPQ2d at 1196.
Specifically, one of the proper form of Markush grouping should recite “selected from the group consisting of..’ (see MPEP 2173.05(h)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0337426 to Huang in view of Or-Bach et al. (US 2020/0013791, hereinafter Or-Bach).
With respect to claim 1, Huang discloses a 3D cell structure (e.g., non-volatile 3D AND flash memory, see the annotated Figs. 1D-1E below) (Huang, Figs. 1A-1B, 1E-1D, 3I, ¶0020-¶0036, ¶0054-¶0070), comprising:
a vertical bit line (BL) (e.g., 32b) (Huang, Figs. 1H, 3I, ¶0033, ¶0036);
a vertical source line (SL) (e.g., 32a) (Huang, Figs. 1H, 3I, ¶0033, ¶0036);
a channel body (16) (Huang, Figs. 1E-1D, 3I, ¶0033, ¶0035) surrounding and connected to a portion of the BL (32b) and a portion of the SL (32a);
an insulator (54) (Huang, Figs. 1E-1D, 3I, ¶0031, ¶0035) coupled to and surrounding the channel body (16);
a first gate dielectric layer (e.g., 12/36, surrounding a top gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) coupled to a top surface of the insulator (54) and the channel body (16), and surrounding top portions of the BL (32b) and the SL (32a);
a second gate dielectric layer (e.g., 12/36, surrounding a gate layer 38 underlying the top gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) coupled to a bottom surface of the insulator (54) and the channel body (36), and surrounding bottom portions of the BL (32b) and the SL (32a);
a front gate (e.g., the top gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) connected to a top surface of the first gate dielectric layer (12/36); and
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a back gate (e.g., the gate layer 38 underlying the top gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) connected to a bottom surface of the second gate dielectric layer (12/36).
Further, Huang does not specifically disclose a floating body filling any space in between the BL and SL.
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However, Or-Bach teaches forming non-volatile 3D NOR flash memory (e.g., which is also called AND architecture, see the annotated Figs. 31J, 42, and 43F below) (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0009, ¶0106, ¶0167, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) constructed as a floating body memory (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) including isolated channel layers having a ring shape or donut shape (Or-Bach, Figs. 31J, 42, 43F, ¶0269) with isolated channel region per layer along vertical Z direction, wherein a floating body includes an isolated channel (4062/4065/4066 in Figs. 31I-31J or 5216 in Fig. 43F) (Or-Bach, Figs. 31H-31J, 43F, ¶0235-¶0237, ¶0273) filling any space in between the BL (4072 or 5244, S/D pillar in Figs. 31J and 43F) and SL (4071or 5244, S/D pillar in Figs. 31J and 43F), to provide improved 3D NOR memory including enhanced channel structure with no silicon channel between inter wordline regions such that no leakage path through an ungated region (Or-Bach, ¶0219-¶0222, ¶0269).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang by forming a floating body channel having a ring shape with isolated channel region per layer as taught by Or-Bach to have the 3D cell structure, comprising: a floating body filling any space in between the BL and SL, in order to provide improved 3D NOR memory including enhanced channel structure with no silicon channel between inter wordline regions such that no leakage paths through an ungated region (Or-Bach, ¶0009, ¶0106, ¶0219-¶0222, ¶0269).
Regarding claims 2 and 4-5, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the BL (32b) (Huang, Figs. 1E-1D, 3I, ¶0033) and SL (32a) comprises doped polysilicon material, but does not specifically disclose that the BL and SL comprise heavily doped N+ or P+ polysilicon semiconductor material (as claimed in claim 2); wherein the floating body comprises a lightly doped semiconductor material having an opposite type of doping from the BL and SL (as claimed in claim 4); wherein the floating body comprises a heavily doped semiconductor material having a same type of doping as the BL and SL (as claimed in claim 5).
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (Or-Bach, Figs. 41-42, ¶0268, ¶0269), wherein the BL (e.g., S/D pillars 5004/5002) and SL (e.g., S/D pillars 5002/5004) comprise heavily doped N+ polysilicon (e.g., N++ polysilicon material) semiconductor material, and the channel material is boron doped or undoped polysilicon material (Or-Bach, ¶0232, ¶0268) having an opposite type (p-type) of doping from the BL and SL (e.g., N++ polysilicon), to form junction transistor structure; or the channel material comprises a heavily doped semiconductor material (N++ polysilicon) having a same type of doping as the BL and SL, to form junction less transistor structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming S/D (bit/source) pillars and a floating body channel having specific materials based on functionality of the device as taught by Or-Bach to have the 3D cell structure, wherein the BL and SL comprise heavily doped N+ or P+ polysilicon semiconductor material (as claimed in claim 2); wherein the floating body comprises a lightly doped semiconductor material having an opposite type of doping from the BL and SL (as claimed in claim 4); wherein the floating body comprises a heavily doped semiconductor material having a same type of doping as the BL and SL (as claimed in claim 5), in order to provide improved 3D NOR memory including enhanced channel structure and a specific architecture for various applications (Or-Bach, ¶0009, ¶0219-¶0222, ¶0268-¶0269).
Regarding claim 3, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the BL (32b) and SL (32a) (Huang, Figs. 1E-1D, 3I, ¶0033) comprises metal cores.
Regarding claim 6, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the insulator (54, silicon oxide) (Huang, Figs. 1E-1D, 3I, ¶0054) comprises oxide material.
Regarding claim 7, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the first and second gate dielectric layers (12/36) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0069) comprise Hi-K material (e.g., blocking layer 36 includes high dielectric constant material such as hafnium oxide).
Regarding claim 8, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the first and second gate dielectric layers (12/36) comprise charge-trapping layers (e.g., charge storage layer 12 includes silicon nitride or the materials capable of trapping charges) (Huang, Figs. 1E-1D, 3I, ¶0034), but does not specifically disclose charge-trapping layers selected from a set comprising oxide-nitride-oxide (ONO) layers, oxide-nitride-oxide-nitride-oxide (ONONO) layers, and oxide-nitride (ON) layers.
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (Or-Bach, Figs. 41-42, 31A-31J, ¶0156, ¶0232, ¶0268, ¶0269), wherein charge-trapping layers comprise O/N/O stack (4032) including oxide layers and nitride layer, to form a charge trap memory.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming charge-trapping layers comprising O/N/O stack as taught by Or-Bach to have the 3D cell structure, wherein charge-trapping layers selected from a set comprising oxide-nitride-oxide (ONO) layers, in order to provide improved 3D NOR memory including enhanced channel structure and a specific architecture for various applications (Or-Bach, ¶0009, ¶0219-¶0222, ¶0268-¶0269).
Regarding claim 9, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the front gate and the back gate comprise metal (e.g., tungsten) (Huang, Figs. 1E-1D, 3I, ¶0069).
Regarding claim 10, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 1. Further, Huang discloses the 3D cell structure, wherein the BL and SL are parallel to each other, but does not specifically disclose that the BL and SL form a channel length having a range of 1nm (nanometer) to 1um (micro-meter).
However, Or-Bach teaches forming 3D NOR memory (Or-Bach, Figs. 31H-31J, 43A-43F, ¶0249, ¶0242) having a channel width in Y direction of 20 nm or more or between 40 nm and 60 nm or more, wherein the distance between the S/D pillars (the BL and the SL) that defines the channel length is greater than 10 nm or greater than 50 nm. In Or-Bach, the longer effective channel length improves short channel effects.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming 3D NOR memory having specific distance between the S/D pillars (the BL and the SL) as taught by Or-Bach to have the 3D cell structure, wherein the BL and SL form a channel length having a range of 1nm (nanometer) to 1um (micro-meter), in order to provide improved 3D NOR memory including longer effective channel length to improve short channel effects (Or-Bach, ¶0009, ¶0242, ¶0249, ¶0268-¶0269).
With respect to claim 11, Huang discloses a 3D cell structure (e.g., non-volatile 3D AND flash memory, see the annotated Figs. 1D-1E above) (Huang, Figs. 1A-1B, 1E-1D, 3I, ¶0020-¶0036, ¶0054-¶0070), comprising:
a vertical bit line (BL) (e.g., 32b) (Huang, Figs. 1E-1D, 3I, ¶0033, ¶0036);
a vertical source line (SL) (e.g., 32a) (Huang, Figs. 1E-1D, 3I, ¶0033, ¶0036);
a channel body (16) (Huang, Figs. 1E-1D, 3I, ¶0033, ¶0035) surrounding and connected to a portion of the BL (32b) and a portion of the SL (32a);
a gate dielectric layer (e.g., 12/36, surrounding a top gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) coupled to and surrounding the channel body (16);
a gate (e.g., the gate layer 38) (Huang, Figs. 1E-1D, 3I, ¶0034, ¶0035) surrounding the gate dielectric layer (12/36); and
a first insulating layer (e.g., upper insulator 54) (Huang, Figs. 1E-1D, 3I, ¶0031, ¶0035) coupled to a top surface of the gate dielectric layer (12/36) and the channel body (16), and surrounding top portions of the BL (32b) and the SL (32a); and
a second insulating layer (e.g., bottom insulator 54) (Huang, Figs. 1E-1D, 3I, ¶0031, ¶0035) coupled to a bottom surface of the gate dielectric layer (12/36) and the channel body, and surrounding bottom portions of the BL and the SL.
Further, Huang does not specifically disclose a floating body filling any space in between the BL and SL.
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (e.g., which is also called AND architecture, see the annotated Figs. 31J, 42, and 43F above) (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0009, ¶0106, ¶0167, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) constructed as a floating body memory (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) including isolated channel layers having a ring shape or donut shape (Or-Bach, Figs. 31J, 42, 43F, ¶0269) with isolated channel region per layer along vertical Z direction, wherein a floating body includes an isolated channel (4062/4065/4066 in Figs. 31I-31J or 5216 in Fig. 43F) (Or-Bach, Figs. 31H-31J, 43F, ¶0235-¶0237, ¶0273) filling any space in between the BL (4072 or 5244, S/D pillar in Figs. 31J and 43F) and SL (4071or 5244, S/D pillar in Figs. 31J and 43F), to provide improved 3D NOR memory including enhanced channel structure with no silicon channel between inter wordline regions such that no leakage path through an ungated region (Or-Bach, ¶0219-¶0222, ¶0269).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang by forming a floating body channel having a ring shape with isolated channel region per layer as taught by Or-Bach to have the 3D cell structure, comprising: a floating body filling any space in between the BL and SL, in order to provide improved 3D NOR memory including enhanced channel structure with no silicon channel between inter wordline regions such that no leakage paths through an ungated region (Or-Bach, ¶0009, ¶0106, ¶0219-¶0222, ¶0269).
Regarding claims 12 and 14-15, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the BL (32b) (Huang, Figs. 1E-1D, 3I, ¶0033) and SL (32a) comprises doped polysilicon material, but does not specifically disclose that the BL and SL comprise heavily doped N+ or P+ polysilicon semiconductor material (as claimed in claim 12); wherein the floating body comprises a lightly doped semiconductor material having an opposite type of doping from the BL and SL (as claimed in claim 14); wherein the floating body comprises a heavily doped semiconductor material having a same type of doping as the BL and SL (as claimed in claim 15).
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (Or-Bach, Figs. 41-42, ¶0268, ¶0269), wherein the BL (e.g., S/D pillars 5004/5002) and SL (e.g., S/D pillars 5002/5004) comprise heavily doped N+ polysilicon (e.g., N++ polysilicon material) semiconductor material, and the channel material is boron doped or undoped polysilicon material (Or-Bach, ¶0232, ¶0268) having an opposite type (p-type) of doping from the BL and SL (e.g., N++ polysilicon), to form junction transistor structure; or the channel material comprises a heavily doped semiconductor material (N++ polysilicon) having a same type of doping as the BL and SL, to form junction less transistor structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming S/D (bit/source) pillars and a floating body channel having specific materials based on functionality of the device as taught by Or-Bach to have the 3D cell structure, wherein the BL and SL comprise heavily doped N+ or P+ polysilicon semiconductor material (as claimed in claim 12); wherein the floating body comprises a lightly doped semiconductor material having an opposite type of doping from the BL and SL (as claimed in claim 14); wherein the floating body comprises a heavily doped semiconductor material having a same type of doping as the BL and SL (as claimed in claim 15), in order to provide improved 3D NOR memory including enhanced channel structure and a specific architecture for various applications (Or-Bach, ¶0009, ¶0219-¶0222, ¶0268-¶0269).
Regarding claim 13, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the BL (32b) and SL (32a) (Huang, Figs. 1E-1D, 3I, ¶0033) comprises metal cores.
Regarding claim 16, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the first and second insulating layers (54, silicon oxide) (Huang, Figs. 1E-1D, 3I, ¶0054) comprise oxide material.
Regarding claim 17, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the gate comprises metal (e.g., tungsten) (Huang, Figs. 1E-1D, 3I, ¶0069).
Regarding claim 18, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the gate dielectric layer (12/36) comprises charge-trapping layers (e.g., charge storage layer 12 includes silicon nitride or the materials capable of trapping charges) (Huang, Figs. 1E-1D, 3I, ¶0034), but does not specifically disclose charge-trapping layers selected from a set comprising oxide-nitride-oxide (ONO) layers, oxide-nitride-oxide-nitride-oxide (ONONO) layers, and oxide-nitride (ON) layers.
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (Or-Bach, Figs. 41-42, 31A-31J, ¶0156, ¶0232, ¶0268, ¶0269), wherein charge-trapping layers comprise O/N/O stack (4032) including oxide layers and nitride layer, to form a charge trap memory.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming charge-trapping layers comprising O/N/O stack as taught by Or-Bach to have the 3D cell structure, wherein charge-trapping layers selected from a set comprising oxide-nitride-oxide (ONO) layers, in order to provide improved 3D NOR memory including enhanced channel structure and a specific architecture for various applications (Or-Bach, ¶0009, ¶0219-¶0222, ¶0268-¶0269).
Regarding claim 19, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the BL and SL are parallel to each other, but does not specifically disclose that the BL and SL form a channel length having a range of 1nm (nanometer) to 1um (micro-meter).
However, Or-Bach teaches forming 3D NOR memory (Or-Bach, Figs. 31H-31J, 43A-43F, ¶0249, ¶0242) having a channel width in Y direction of 20 nm or more or between 40 nm and 60 nm or more, wherein the distance between the S/D pillars (the BL and the SL) that defines the channel length is greater than 10 nm or greater than 50 nm. In Or-Bach, the longer effective channel length improves short channel effects.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming 3D NOR memory having specific distance between the S/D pillars (the BL and the SL) as taught by Or-Bach to have the 3D cell structure, wherein the BL and SL form a channel length having a range of 1nm (nanometer) to 1um (micro-meter), in order to provide improved 3D NOR memory including longer effective channel length to improve short channel effects (Or-Bach, ¶0009, ¶0242, ¶0249, ¶0268-¶0269).
Regarding claim 20, Huang in view of Or-Bach discloses forming the 3D cell structure of claim 11. Further, Huang discloses the 3D cell structure, wherein the 3D cell structure forms a 3D AND-type cell, but does not specifically disclose a 3D NOR-type cell.
However, Or-Bach teaches forming non-volatile 3D NOR flash memory (e.g., which is also called AND architecture) (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0009, ¶0106, ¶0167, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) constructed as a floating body memory (Or-Bach, Figs. 31H-31J, 42, 43F, 44A-44B, ¶0219-¶0222, ¶0230-¶0232, ¶0234-¶0237, ¶0269-¶0276) including isolated channel layers having a ring shape or donut shape (Or-Bach, Fig. 42, ¶0269) with isolated channel region per layer along vertical Z direction, to provide improved 3D NOR memory including enhanced channel structure with no silicon channel between inter wordline regions such that no leakage path through an ungated region (Or-Bach, Figs. 31H-31J, ¶0219-¶0222, ¶0269).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the 3D cell structure of Huang/Or-Bach by forming 3D memory including stacked isolated channel regions configured as NOR-type memory as taught by Or-Bach to have the 3D cell structure, wherein the 3D cell structure forms a 3D NOR-type cell, in order to provide improved 3D NOR memory including enhanced channel structure (Or-Bach, ¶0009, ¶0106, ¶0219-¶0222, ¶0269).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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