Prosecution Insights
Last updated: August 17, 2026
Application No. 18/597,930

DISPLAY DEVICE AND ELECTRONIC APPARATUS

Non-Final OA §103
Filed
Mar 07, 2024
Priority
Mar 10, 2023 — JP 2023-037671
Examiner
BOWEN, ADAM S
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seiko Epson Corporation
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allowance Rate
705 granted / 731 resolved
+28.4% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
16 currently pending
Career history
748
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
46.8%
+6.8% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 731 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/07/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (2024/0162394) in view of Nakamura et al. (2023/0317894). Re claim 1, Li teaches a display device (Fig. 1), comprising: a first substrate (11); a second substrate (40) disposed so as to be opposed to the first substrate (11); a first light-emitting element (21, “left”) and a second light-emitting element (21, “right”) provided between the first substrate (11) and the second substrate (40); a driving circuit (12) provided at the first substrate (11) and configured to drive the first light-emitting element and the second light-emitting element [62-65]; a first insulation section (30, “left section”) having elasticity and provided between the first substrate (11) and the first light-emitting element (21); a second insulation section (30, “right section”) having elasticity and provided between the first substrate (11) and the second light-emitting element (21); a first conductive layer [65] provided between the first insulation section (30) and the first light-emitting element (21. “left”); and a second conductive layer [65] provided between the second insulation section (30) and the second light-emitting element (21, “right”); and a coupling portion (60) configured to couple the first substrate (11) and the second substrate (40). Li does not explicitly teach the first conductive layer being configured to be electrically coupled to the driving circuit and be pressed against the first light-emitting element by the first insulation section; the second conductive layer being configured to be electrically coupled to the driving circuit and be pressed against the second light-emitting element by the second insulation section. Nakamura teaches a display device (Fig. 1A) comprising a first conductive layer (42, “15R”) being configured to be electrically coupled to the driving circuit (52, “15R”) and be pressed against a first light-emitting element (31, “15R”) by a first insulation section (13, “15R”); a second conductive layer (42, “15G”) being configured to be electrically coupled to the driving circuit (52, “15G”) and be pressed against a second light-emitting element (31, “15G”) by a second insulation section (13, “15G”). Therefore, it would have been obvious to one of ordinary skill in the art, as of the effective filling date of the claimed invention, to modify Li as taught by Nakamura since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made. Re claim 4, Li in view of Nakamura teaches the display device according to claim 1, wherein the first insulation section (30, Li) and the second insulation section (30, Li) continue with each other (Fig. 1, Li). Re claim 6, Li in view of Nakamura teaches the display device according to claim 1 comprising: a first metal layer (22, Li) provided between the first light-emitting element (21, Li) and the driving circuit (12, Li) and having a light shielding property ([65], Li); and a second metal layer (22, Li) provided between the second light-emitting element (21, Li) and the driving circuit (12, Li) and having a light shielding property ([65], Li). Re claim 7, Li in view of Nakamura teaches the display device according to claim 6, wherein a constant potential is applied to the first metal layer and the second metal layer ([65], Li). Re claim 8, Li in view of Nakamura teaches the display device according to claim 1, further comprising: a spacer member (70, Li) provided between the first substrate (11, Li) and the second substrate (40, Li) and being in contact with the first substrate (11, Li) and the second substrate (40, Li), wherein the spacer member (70, Li) surrounds the first light-emitting element (21, Li) and the second light-emitting element (21, Li), and the coupling portion (60, Li) is joined to the first substrate (11, Li) through a glue layer (80, Li). Re claim 9, Li in view of Nakamura teaches the electronic apparatus, comprising the display device according to claim 1 ([61-62], Li). Allowable Subject Matter Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 2, Li in view of Nakamura teaches the display device according to claim 1, yet remains explicitly silent to wherein a constant potential is applied to the coupling portion. Claim 3 is objected to for at least depending from objected claim 2. Re claim 5, Li in view of Nakamura teaches the display device according to claim 1, yet remains explicitly silent to wherein the first insulation section and the second insulation section have a light shielding property. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /ADAM S BOWEN/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Mar 07, 2024
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12696524
STACKED TRANSISTOR ISOLATION FEATURES AND METHODS OF FORMING THE SAME
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Patent 12690406
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Patent 12685227
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2y 9m to grant Granted Jul 14, 2026
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2y 9m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+2.4%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 731 resolved cases by this examiner. Grant probability derived from career allowance rate.

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