Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18598099 filed on 03/07/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 16-23 the reply filed on 7/2/206 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16, 23 recites the limitation “dielectric material lining and thereby defining the emitter window”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The highlighted limitation has not been defined before and lacks proper antecedent basis. Furthermore, it is unclear what this limitation is referring to (e.g. is the dielectric material lining defining the emitter window or is there some other layer defining the emitter window). For purpose of examination, the dielectric material lining is interpreted as defining the emitter window.
Claim 16, 23 recites the limitation “further silicon material within the emitter window and providing an n-emitter base region”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The specification does not appear to define an emitter base region and it is unclear what the highlighted limitation is referring to. For purpose of examination, the silicon material is considered to be providing an emitter region per specification (paragraph 0028) of the instant application.
Claim 16, 23 recites the limitation “providing electrical contact to the n-type emitter region”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The highlighted limitation has not been defined before and lacks proper antecedent basis. Furthermore, this appears to be contradictory to the specification as paragraph 0028 discloses “Electrical connection is provided to the emitter region of the device by an emitter contact, as shown schematically at 172” where element 172 is different from element 160 which is the emitter region.
Claims 17-22 are also rejected under 112(b) as they depend on base claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Magnee et al. (US 2020/0075585).
Regarding independent claim 16, Magnee et al. teach a silicon (Si) bipolar junction transistor (BJT) device comprising:
an n-type collector region (Fig. 6, element 630, paragraph 0065) grown epitaxially (The limitation “grown epitaxially is a product by process limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP §2113) on a silicon substrate (Figs. 1 & 6, paragraph 0055);
an implanted p-type base region (Fig. 6, element 620, paragraph 0065) formed in a top region of the collector region;
a dielectric layer (Figs. 1 & 6, element 300, paragraph 0054) and a layer stack comprising silicon germanium (SiGe) (Figs. 1 & 6, element 400, paragraph 0056), formed non-adjacent to an emitter window (Figs. 5 & 6, element 370, paragraph 0063) and on a part of the base region (Fig. 6);
a polysilicon layer (Figs. 5 & 6, element 500, paragraph 0059), over the dielectric layer, between the dielectric layer and the emitter window and between the layer stack comprising SiGe and the emitter window, the polysilicon layer for providing electrical contact to the base region;
dielectric material lining (Figs. 5 & 6, element 370, paragraph 0063) and thereby defining the emitter window; and
further silicon material (Figs. 5 & 6, element 520, paragraph 0063) within the emitter window and providing an n-emitter base region, and providing electrical contact to the n-type emitter region (Fig. 6, element 610, paragraph 0065),
wherein the polysilicon layer comprises non-uniformities (due to typical process variations (such as deposition drift, etching error, surface contamination etc.) in wafer fabrication there would naturally be non-uniformities) adjacent at least a lower part of the dielectric layer.
Regarding claim 17, Magnee et al. teach wherein the non-uniformities comprise micro-voids (typical process variations (such as deposition drift, etching error, surface contamination etc.) in wafer fabrication would cause micro-voids).
Regarding claim 18, Magnee et al. teach wherein the non-uniformities comprise silicon material having a different doping level than a remainder of the polysilicon layer (there would naturally be a doping difference in different regions due to diffusion variation).
Regarding claim 19, Magnee et al. teach wherein the non-uniformities comprise micro-voids (typical process variations (such as deposition drift, etching error, surface contamination etc.) in wafer fabrication would cause micro-voids).
Regarding claim 20, Magnee et al. teach wherein the polysilicon layer adjacent the implanted p-type base region is not epitaxial therewith (This is a product by process limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP §2113).
Regarding claim 21, Magnee et al. teach wherein the non-uniformities comprise micro-voids (typical process variations (such as deposition drift, etching error, surface contamination etc.) in wafer fabrication would cause micro-voids).
Regarding claim 22, Magnee et al. teach wherein an upper surface of the implanted p-type base region has a uniform height (Figs. 4-6).
Regarding independent claim 23, Magnee et al. teach a semiconductor product comprising:
a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) (Fig. 6, element 100, paragraph 0053); and
a silicon bipolar junction transistor (BJT) device (Fig. 6, element 200, paragraph 0053) that includes an n-type collector region (Fig. 6, element 630, paragraph 0065) grown epitaxially (The limitation “grown epitaxially is a product by process limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP §2113) on a silicon substrate (Figs. 1 & 6, paragraph 0055),
an implanted p-type base (Fig. 6, element 620, paragraph 0065) region formed in a top region of the collector region,
a dielectric layer (Figs. 1 & 6, element 300, paragraph 0054) and a layer stack comprising silicon germanium (SiGe) (Figs. 1 & 6, element 400, paragraph 0056), formed non-adjacent to an emitter window (Figs. 5 & 6, element 370, paragraph 0063) and on a part of the base region,
a polysilicon layer (Figs. 5 & 6, element 500, paragraph 0059), over the dielectric layer, between the dielectric layer and the emitter window and between the layer stack comprising SiGe and the emitter window, the polysilicon layer for providing electrical contact to the base region,
dielectric material lining (Figs. 5 & 6, element 370, paragraph 0063) and thereby defining the emitter window, and
further silicon material Figs. 5 & 6, element 520, paragraph 0063) within the emitter window and providing an n-emitter base region, and providing electrical contact to the n-type emitter region (Fig. 6, element 610, paragraph 0065),
wherein the polysilicon layer comprises non-uniformities (due to typical process variations (such as deposition drift, etching error, surface contamination etc.) in wafer fabrication there would naturally be non-uniformities) adjacent at least a lower part of the dielectric layer.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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