DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. RESPONSE TO ELECTION
Applicant’s election without traverse of requirement for restriction/election dated 2/24/26 in the reply filed on 4/13/26 is acknowledged. The Examiner notes the election of group II (claims 8-20) and the cancellation of group I (claims 1-7).
2. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 3/7/24, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keller (US 20080077813) in view of Boyd (US 20190026226).
With respect to claim 8, the Keller reference teaches a memory component, comprising:
an array to store a plurality of cache information entries, each cache information entry comprising a tag field, a cache line, and at least one cache line status indicator; (e.g. fig. 2, data cache 34; and paragraph 30, where the cache tag memory 38 is coupled to the data memory 40, which is coupled to provide/receive data (in the event of a hit in the data cache 34) to/from the core 32. The cache tag memory 38 is further coupled to receive snoop addresses (and flush address info) from the mux 50 and to provide a snoop hit dirty indication and evict address to the MRB address buffer 44. The mux 50 has an input coupled to the MRB address buffer 44 to receive a snoop address, and an input from the flush control unit 42 to receive a flush index and way. The mux select control is provided by the flush control unit 42. The MRB data buffer 46 is coupled to receive and provide data from/to the data memory 40 and to receive and provide data on the data portion of the interconnect 20)
a command/address interface to receive a first write access command, in association with a first tag query value, to access a first cache information entry comprising a first tag value, a first cache line, and a first cache line status indicator; (e.g. fig. 2, cache tag 38; and paragraph 31, where each cache block storage location comprises a memory location in the cache tags memory 38 and a memory location in the data memory 40. The cache tags memory 38 stores a tag locating the corresponding cache block in memory. The tag may generally include a portion of the address that excludes the cache offset portion and the portion used to index the data cache 34, in set associative or direct mapped embodiments)
a buffer to, based on the first cache line status indicator, store the first cache line; (e.g fig. 2, MRB data buffer 46; and paragraph 30, where cache tag memory 38 is further coupled to receive snoop addresses (and flush address info) from the mux 50 and to provide a snoop hit dirty indication and evict address to the MRB address buffer 44. The mux 50 has an input coupled to the MRB address buffer 44 to receive a snoop address, and an input from the flush control unit 42 to receive a flush index and way. The mux select control is provided by the flush control unit 42. The MRB data buffer 46 is coupled to receive and provide data from/to the data memory 40 and to receive and provide data on the data portion of the interconnect 20) and
a data interface to, based on an event indicator, transmit the first cache line stored in the buffer. (e.g. fig. 2, interconnect 20; paragraph 17, where the agent coupled to the interconnect 20 may communicate via transactions having address, response, and data phases on the interconnect 20; and paragraph 30, where mux select control is provided by the flush control unit 42. The MRB data buffer 46 is coupled to receive and provide data from/to the data memory 40 and to receive and provide data on the data portion of the interconnect 20)
However, the Keller reference does not explicitly teach the array is a dynamic random access memory (DRAM).
The Boyd reference teaches it is conventional to have the array be a dynamic random access memory (DRAM). (paragraph 15, where a DRAM based cache
speeds up removable media accesses for read operations)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Keller reference to have the array be a dynamic random access memory (DRAM), as taught by the Boyd reference.
The suggestion/motivation for doing so would have been to speed up removable media accesses for read operations. (Boyd, paragraph 15)
Therefore it would have been obvious to combine the Keller and Boyd references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 9, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the event indicator is associated with a command, received via the command/address interface, to access the first cache line from the buffer. (Keller, paragraph 30, where cache tag memory 38 is further coupled to receive snoop addresses (and flush address info) from the mux 50 and to provide a snoop hit dirty indication and evict address to the MRB address buffer 44. The mux 50 has an input coupled to the MRB address buffer 44 to receive a snoop address, and an input from the flush control unit 42 to receive a flush index and way. The mux select control is provided by the flush control unit 42. The MRB data buffer 46 is coupled to receive and provide data from/to the data memory 40 and to receive and provide data on the data portion of the interconnect 20)
With respect to claim 10, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the event indicator is associated with a sequence of commands received via the command/address interface. (Keller, paragraph 30, where cache tag memory 38 is further coupled to receive snoop addresses (and flush address info) from the mux 50 and to provide a snoop hit dirty indication and evict address to the MRB address buffer 44. The mux 50 has an input coupled to the MRB address buffer 44 to receive a snoop address, and an input from the flush control unit 42 to receive a flush index and way. The mux select control is provided by the flush control unit 42. The MRB data buffer 46 is coupled to receive and provide data from/to the data memory 40 and to receive and provide data on the data portion of the interconnect 20)
With respect to claim 11, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the event indicator is associated with a command, received via the command/address interface, that results a period of time where data to and from the DRAM array is not to be communicated via the data interface. (Keller, paragraph 30, where flush control unit 42 may also be configured to interrupt flush operation to permit a snoop hit to be serviced in the data cache 34 (responsive to the snoop hit signal from the snoop tag 48, in the illustrated embodiment). The flush control unit 42 may select the snoop address from the MRB address buffer 44 for one access (e.g. one clock cycle) in response to the snoop hit. The selection of the snoop address may be delayed from the assertion of the snoop hit by one or more clock cycles to permit the snoop address to be written to the MRB address buffer 44 and to be available on the snoop address input to the mux 50)
With respect to claim 12, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the sequence of commands comprises a write command followed by a read command. (Keller, paragraph 32, where in the event of a cache miss, a fill request for the data cache 34 may be queued in the MRB address buffer 44, and the missing cache block may be filled to the data cache 34. When the missing cache block is filled into the data cache 34, another cache block may be evicted from the data cache 34)
With respect to claim 13, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the sequence of commands results a period of time where data from the DRAM array is not to be communicated via the data interface. (Keller, paragraph 30, where flush control unit 42 may also be configured to interrupt flush operation to permit a snoop hit to be serviced in the data cache 34 (responsive to the snoop hit signal from the snoop tag 48, in the illustrated embodiment). The flush control unit 42 may select the snoop address from the MRB address buffer 44 for one access (e.g. one clock cycle) in response to the snoop hit. The selection of the snoop address may be delayed from the assertion of the snoop hit by one or more clock cycles to permit the snoop address to be written to the MRB address buffer 44 and to be available on the snoop address input to the mux 50)
With respect to claim 14, the combination of the Keller and Boyd references teaches the memory component of claim 8, wherein the first cache line status indicator is associated with the first write access command being directed to a second cache line that is not the first cache line and being associated with the first cache line being in a modified state. (Keller, paragraph 22, where flushing the data cache may include writing any cache blocks that have been modified by the processor in the cache (and thus the copy in the memory system and/or the L2 cache 14, if any, is not the most recent copy) out of the processor)
Claims 15-20 are the method implementation of claims 8-14, and rejected under a similar rationale as shown in the rejections above.
4. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Solomon (US 6681293), which teaches a method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the "shared state" that allows reading of the data, but does not permit modifications to the data (i.e., modifications that would have to be written back to memory). If it is desired to modify the data, a directory facility will issue a purge to all caches of the shared-state data for that cache line, and then the processor that wants to modify the data will request an exclusive-state copy to be fetched to its lower-level cache and to all intervening levels of cache. Later, when the data in the lower cache level is modified, the modified data can be moved back to the original memory from the caches. In some embodiments, a purge of all shared-state copies of the first cache-line data from any and all caches having copies thereof is performed as a prerequisite to doing this exclusive-state fetch.
5. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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