Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al (US 20200135472).
Regarding Claim 9, Jang teaches A method (200, Fig. 25, para [0009]), comprising: forming an insulating material over a substrate (22, Fig. 2, para [0015]); depositing a gate dielectric layer on the insulating material (52, Fig. 7B, para [0027])); depositing a gate electrode layer (56, Fig. 7B, para [0026]) on the gate dielectric layer (52, Fig. 7B, para [0027]); forming a mask structure on the gate electrode layer (62 & 64 & 66 & 72, Fig. 12B, para [0029] & [0031]-[0033]); performing a cyclic process to form an opening through the mask structure and the gate electrode layer (74, Fig. 13-18, para [0034]-[0040]); performing a trim process to remove portions of the mask structure (62 & 64 & 66 & 72 & 212-214, Fig. 12-13 & Fig. 25, para [0029] & [0031]-[0034]), wherein the trim process comprises introducing an etchant and a carbon-containing gas (214, Fig. 25, para [0034]-[0035]); and filling the opening with a dielectric material (82 & 226, Fig, 20A & Fig. 25, para [0049]).
Claim Rejections - 35 USC § 103
Claim(s) 1, 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20200135472) in view of Lee et al (US 20140167228 ).
Regarding Claim 1, Jang teaches A method (200, Fig. 25, para [0009]), comprising: forming a fin structure over a substrate (24, Fig. 2, para [0016]); forming an insulating material adjacent the fin structure (22, Fig. 2, para [0015]); depositing a gate dielectric layer over the fin structure and the insulating material (52, Fig. 7B, para [0027]); depositing a gate electrode layer on the gate dielectric layer (56, Fig. 7B, para [0027]); forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material by a cyclic process (74, Fig. 19B, para [0040]), wherein the cyclic process comprises (no reference element, Fig. 13-19C, para [0039]): and filling the opening with a dielectric material (82, Fig. 20B, para [0049]).
Jang does not explicitly teach wherein performing a first number of cycles, wherein each cycle of the first number of cycles includes a first main etch process having a first plasma bias voltage; and performing a second number of cycles, wherein each cycle of the second number of cycles includes a second main etch process having a second plasma bias voltage substantially greater than the first plasma bias voltage.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of predicted success, Lee teaches wherein performing a first number of cycles (108, Fig. 1, para [0015]), wherein each cycle of the first number of cycles includes a first main etch process (108, Fig. 1, para [0023]) having a first plasma bias voltage (108, Fig. 1, para [0023]); and performing a second number of cycles (120, Fig. 1, para [0015]), wherein each cycle of the second number of cycles includes a second main etch process (120, Fig. 1, para [0025]) having a second plasma bias voltage substantially greater than the first plasma bias voltage (120, Fig. 1, para [0025]).
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to implement this cyclic process in Jang in view of Lee for the advantage of improving the etching aspect ratio (see para [0002]).
Regarding Claim 3, Jang and Lee teach The method of claim 1 (Jang, 200, Fig. 25, para [0009]), wherein the first plasma bias voltage ranging from about 150 V to about 250 V (no reference number, Fig. 3, para [0023]), and the second plasma bias voltage ranging from about 800 V to about 1200 V (no reference number, Fig. 3, para [0025]).
Regarding Claim 4, Jang teaches The method of claim 1 (200, Fig. 25, para [0009]),
Jang does not explicitly teach wherein the first number of cycles includes more cycles than the second number of cycles.
However, we know that Jang describes a cylindrical process (Fig. 25, para [0039]) which coincides with the first step and the second step coincides with filling the opening with a dielectric material (element 226 in Fig. 25). It is implied that the first step is performed more times than the second step.
Regarding Claim 5, Jang teaches The method of claim 1 (200, Fig. 25, para [0009]), wherein each cycle of the first number of cycles comprises (218-222, Fig. 25, para [0036]-[0038]): depositing a layer on the gate electrode layer (76, Fig. 14, para [0036]); oxidizing the layer to form an oxide layer (76, Fig. 14, para [0036]; element 76 includes SiO2 which by definition must be oxidized); removing a portion of the oxide layer (76, Fig. 15, para [0037]); and performing the first main etch process to remove a portion of the gate electrode layer (74, Fig. 16, para [0038]).
Regarding Claim 6, Jang teaches The method of claim 5 (218-222, Fig. 25, para [0036]-[0038]), wherein the first main etch process uses one or more chlorine-containing etchants (218-222, Fig. 25, para [0035]).
Regarding Claim 7, Jang teaches The method of claim 6 (218-222, Fig. 25, para [0036]-[0038]), wherein the one or more chlorine-containing etchants comprise BCl3 and Cl2 (218-222, Fig. 25, para [0035]).
Regarding Claim 8, Jang teaches The method of claim 1 (200, Fig. 25, para [0009]), further comprising performing a clean process between the first number of cycles and the second number of cycles (224, Fig. 25, para [0040]-[0043]; describing a wet cleaning process).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20200135472) and Lee et al (US 20140167228 ) as applied to claim1, 3-8 above, and further in view of Ching et al (US 9818872).
Regarding Claim 2, Jang and Lee teach the method of claim 1 (Jang, 200, Fig. 25, para [0009])
Jang and Lee do not explicitly teach wherein the fin structure comprises a plurality of semiconductor layers, and the gate dielectric layer and the gate electrode layer surround a portion of each semiconductor layer of the plurality of semiconductor layers.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of predicted success, Ching teaches wherein the fin structure comprises a plurality of semiconductor layers (Ching, 402, Fig. 6, para (28)), and the gate dielectric layer (Ching, 802, Fig. 9, para {39)) and the gate electrode layer (Ching, 904, Fig. 9, para (42)) surround a portion of each semiconductor layer of the plurality of semiconductor layers (see reference picture below).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to implement a fin structure with a plurality of semiconductor layers to Jang in view of Ching for the advantage of improving gate control (see Ching para {2) for more information).
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20200135472) and in view of the following arguments.
Regarding Claim 10, Jang teaches The method of claim 9 (200, Fig. 25, para [0009]).
Jang does not explicitly teach wherein the trim process is a plasma etch process.
However, Jang does mention the trim process as anisotropic (para [0034]-[0035]) and a dry-plasma etch process is the most common form of anisotropic etching and is well known in the art.
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use a plasma etch process for the advantage of obtaining high aspect ratios.
Regarding Claim 11, The method of claim 10 (200, Fig. 25, para [0009]), wherein a polymer layer is formed on sidewalls of the opening during the trim process (75, Fig. 16, para [0038]).
Regarding Claim 12, Jang teaches The method of claim 11 (200, Fig. 25, para [0009]),
Jang does not explicitly teach wherein further comprising a plasma process to remove the polymer layer after the trim process.
However, However, Jang does mention the trim process as anisotropic (para [0034]-[0035]) and a dry-plasma etch process is the most common form of anisotropic etching and is well known in the art.
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use a plasma process to remove the polymer layer after the trim process since the high aspect ratio from plasma etching would be an advantage in selectively targeting the polymer.
Regarding Claim 13, Jang teaches The method of claim 12 (200, Fig. 25, para [0009]), wherein the plasma process forms an oxygen- containing plasma (no reference number, Fig. 25, para [0038]).
Claim(s) 14-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20200135472) in view of Colombo (US 20070190743), and further in view of Douglas (US 4984039).
Regarding Claim 14, Jang teaches A method (200, Fig. 25, para [0009]), comprising: forming an insulating material over a substrate (22, Fig. 2, para [0015]); depositing a gate dielectric layer on the insulating material (52, Fig. 7B, para [0027]); depositing a gate electrode layer (56, Fig. 7B, para [0026]) on the gate dielectric layer (52, Fig. 7B, para [0027]); forming a mask structure on the gate electrode layer (62 & 64 & 66 & 72, Fig. 12B, para [0029] & [0031]-[0033]); performing a cyclic process to form an opening through the mask structure and the gate electrode layer (74, Fig. 13-18, para [0034]-[0040]), performing a trim process to remove portions of the mask structure (62 & 64 & 66 & 72 & 212-214, Fig. 12-13 & Fig. 25, para [0029] & [0031]-[0034]), and filling the opening with a dielectric material (82 & 226, Fig, 20A & Fig. 25, para [0049]).
Jang does not explicitly teach wherein the opening has a first critical dimension at a top of the mask structure, a second critical dimension at a top of the gate electrode layer, a third critical dimension at a location below the second critical dimension, and the second critical dimension is substantially greater than the first critical dimension and substantially less than the third critical dimension; wherein the first critical dimension is substantially greater than the second critical dimension, and the second critical dimension is substantially greater than the third critical dimension after the trim process.
However, Colombo, in a related field where a person of ordinary skill in the art would have a reasonable expectation of success, teaches a method of etching wherein the opening has a first critical dimension at a top of the mask structure (no reference number, Fig. 9, para [0023]), a second critical dimension at a top of the gate electrode layer (no reference number, Fig. 9, para [0023]), a third critical dimension (no reference number, Fig. 9, para [0023]) at a location below the second critical dimension (see figure below), and the second critical dimension is substantially greater than the first critical dimension and substantially less than the third critical dimension (see figure below).
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Trench bowing is a well known artifact of a plasma etching process; however, in this instance, Colombo teaches a method of etching that does not eliminate bowing but constrains it into acceptable parameters in order to maintain both trench etch process speed but also directionality (see para [0003]-[0006]). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify the process of Jang and include bowing in the trench etch process in view of Colombo for the advantage of increasing etch process speed.
Jang and Colombo do not explicitly teach wherein the first critical dimension is substantially greater than the second critical dimension, and the second critical dimension is substantially greater than the third critical dimension after the trim process.
However, Douglas, in a related field where a person of ordinary skill in the art would have a reasonable expectation of success, teaches a method of etching wherein the first critical dimension (no reference number, Fig, 9b, para (50)) is substantially greater than the second critical dimension (no reference number, Fig, 9b, para (50)), and the second critical dimension is substantially greater than the third critical dimension (no reference number, Fig, 9b, para (50)) after the trim process (see figure below).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify the process of Jang and Colombo and include a tapering process for the trench etching process in view of Douglas, for the advantage of making the process of filling the trench more efficient (see para (12)-(15)).
Regarding Claim 15, Jang and Colombo teach The method of claim 14 (200, Fig. 25, para [0009]), wherein a first angle is formed between a sidewall of the mask structure (Colombo, 3, Fig. 9, para [0014])) exposed in the opening and a top surface of the gate electrode layer (Colombo uses a monocrystalline substrate instead of a gate electrode, however the same techniques can be applied to gate electrode in Jang, 56, Fig. 7B, para [0026]) after the trim process (Colombo, see figure below), and the first angle ranges from about 75 degrees to about 90 degrees (Colombo, α, Fig. 9, para [0023]).
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Regarding Claim 16, Jang and Colombo teach The method of claim 15 (200, Fig. 25, para [0009]), wherein a second angle is formed between a sidewall of the gate electrode layer exposed in the opening and the top surface of the gate electrode layer (Colombo and Douglas use a monocrystalline substrate instead of a gate electrode, however the same techniques can be applied to gate electrode in Jang, 56, Fig. 7B, para [0026])after the trim process (Douglas. Θ, para (50)), and the second angle ranges from about 90 degrees to about 95 degrees (Douglas, see figure below).
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Regarding Claim 17, Jang, Colombo, and Douglas teach The method of claim 16 (200, Fig. 25, para [0009]), wherein the second angle is substantially greater than the first angle (see figures of Colombo and Douglas below).
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Regarding Claim 19, Jang teaches The method of claim 14 (200, Fig. 25, para [0009]), further comprising performing a plasma process to remove a polymer layer from sidewalls of the openings after the trim process.
Jang does not explicitly teach wherein further comprising a plasma process to remove the polymer layer after the trim process.
However, However, Jang does mention the trim process as anisotropic (para [0034]-[0035]) and a dry-plasma etch process is the most common form of anisotropic etching and is well known in the art.
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use a plasma process to remove the polymer layer after the trim process since the high aspect ratio from plasma etching would be an advantage in selectively targeting the polymer.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20200135472), Colombo (US 20070190743), , and Douglas (US 4984039) as applied to claim14-17, 20 above, and further in view of Ching et al (US 9818872).
Regarding Claim 18, Jang teaches The method of claim 14 (Jang, 200, Fig. 25, para [0009]),
Jang does not explicitly teach wherein further comprising forming a plurality of semiconductor layers, wherein the gate dielectric layer and the gate electrode layer surrounds the plurality of semiconductor layers.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of predicted success, Ching teaches wherein the fin structure comprises a plurality of semiconductor layers (Ching, 402, Fig. 6, para (28)), and the gate dielectric layer (Ching, 802, Fig. 9, para {39)) and the gate electrode layer (Ching, 904, Fig. 9, para (42)) surround a portion of each semiconductor layer of the plurality of semiconductor layers (see reference picture below).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to implement a fin structure with a plurality of semiconductor layers to Jang in view of Ching for the advantage of improving gate control (see Ching para {2) for more information).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20080286978
Contains further evidence of bowing or other non-ideal shapes as an artifact of a plasma etching process.
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/ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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