DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 (claims 10 and 18) recites “a plurality of cell channel structures that extend” which should be replaced with “a plurality of cell channel structures that extends”.
Claim 1 (claims 10 and 18) recites “a plurality of gate contact plugs that extend” which should be replaced with “a plurality of gate contact plugs that extends”.
Claim 1 (claims 10 and 18) recites “a plurality of cut insulation layers that extend” which should be replaced with “a plurality of cut insulation layers that extends”.
Claim 10 recites “a plurality of dummy channel structures that extend” which should be replaced with “a plurality of dummy channel structures that extends”.
Claim 16 recites “each the plurality of dummy channel structures” which should be replaced with “each of the plurality of dummy channel structures”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng et al. (hereinafter Cheng) in view of Kang et al. (US 2017/0358590, hereinafter Kang).
With respect to claim 1, Cheng discloses a non-volatile memory device (e.g., NAND memory device) (Cheng, Fig. 4A, ¶0005, ¶0044-¶0077) comprising:
a peripheral circuit structure (416) (Cheng, Fig. 4A, ¶0064) comprising a peripheral circuit (e.g., transistors 418) and a first insulation structure (e.g., interconnect 420 including interlayer dielectric layer (ILD)) (Cheng, Fig. 4A, ¶0066) on the peripheral circuit (416); and
a cell array structure (e.g., NAND memory strings 438) (Cheng, Fig. 4A, ¶0071-¶0073) on the peripheral circuit structure (416), wherein the cell array structure (438) comprises:
a base insulation layer (e.g., pad-out interconnect 450 including ILD) (Cheng, Fig. 4A, ¶0075);
a common source line layer (e.g., a semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the base insulation layer (450);
a buffer insulation layer (e.g., a pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the common source line layer (448);
a cell stack (e.g., memory stack 432) (Cheng, Fig. 4A, ¶0071-¶0074) on the buffer insulation layer (e.g., the pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448), wherein the cell stack (432) comprises a plurality of gate electrodes (434) and a plurality of insulation layers (436), and wherein the plurality of gate electrodes (434) have a nonlinear shape (e.g., a staircase shape) (Cheng, Fig. 4A,);
a plurality of cell channel structures (442/444) (Cheng, Fig. 4A, ¶0072-¶0073) that extend into the cell stack (432) and the buffer insulation layer (e.g., the pad oxide layer between the stack 432 and the semiconductor layer 448) and that are connected to the common source line layer (448); and
a second insulation structure (e.g., interconnect 430 including interlayer dielectric layer (ILD)) (Cheng, Fig. 4A, ¶0070) on the cell stack (432) and that is connected (e.g., through the bonding layer 422/426) to the first insulation structure (420).
Further, Cheng does not specifically disclose a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer; a plurality of cut insulation layers that extend into the base insulation layer, wherein the plurality of cut insulation layers are between the common source line layer and the plurality of protection structures, and wherein the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs.
However, Kang teaches forming a semiconductor memory device (Kang, Fig. 8, ¶0025-¶0078, ¶0095-¶0108) comprising word line contact region (WCTR) (Kang, Fig. 8, ¶0031) including a plurality of gate contact plugs (e.g., plugs MCT in the contact regions CTR1-CTR6) (Kang, Fig. 8, ¶0035, ¶0106) that extend into the cell stack (220) (Kang, Fig. 8, ¶0053-¶0061, ¶0104), wherein each gate contact plug (MCT) of the plurality of gate contact plugs is connected to one corresponding gate electrode (220) of the plurality of gate electrodes; a plurality of protection structures (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) between the plurality of gate contact plugs (MCT) and the base insulation layer (170) (Kang, Fig. 8, ¶0096); a plurality of cut insulation layers (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) that extend into the base insulation layer (170), wherein the plurality of cut insulation layers (304a) are between the common source line layer (CSL) and the plurality of protection structures (185a), and wherein the plurality of cut insulation layers (304a) at least partially surround the plurality of gate contact plugs (MCT).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng by forming a plurality of gate contact plugs as a plurality of word contact plugs of Kang in the word line contact region having a continuous step shape to have the non-volatile memory device comprising: a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer; a plurality of cut insulation layers that extend into the base insulation layer, wherein the plurality of cut insulation layers are between the common source line layer and the plurality of protection structures, and wherein the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claim 2, Cheng in view of Kang discloses the non-volatile memory device of claim 1. Further, Cheng does not specifically disclose that each gate contact plug of the plurality of gate contact plugs extends through the base insulation layer, and each protection structure of the plurality of protection structures at least partially surrounds a portion of one corresponding gate contact plug of the plurality of gate contact plugs.
However, Kang teaches forming the non-volatile memory device, wherein each gate contact plug (MCT) (Kang, Fig. 8, ¶0106) of the plurality of gate contact plugs extends through the base insulation layer (170), and each protection structure (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) of the plurality of protection structures at least partially surrounds a portion of one corresponding gate contact plug (MCT) of the plurality of gate contact plugs.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact plugs as taught by Kang to have the non-volatile memory device, wherein each gate contact plug of the plurality of gate contact plugs extends through the base insulation layer, and each protection structure of the plurality of protection structures at least partially surrounds a portion of one corresponding gate contact plug of the plurality of gate contact plugs, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claim 3, Cheng in view of Kang discloses the non-volatile memory device of claim 2. Further, Cheng does not specifically disclose that the plurality of protection structures extend between the buffer insulation layer and the base insulation layer that is adjacent to the plurality of gate contact plugs, and wherein each protection structure of the plurality of protection structures respectively is connected to one corresponding cut insulation layer of the plurality of cut insulation layers.
However, Kang teaches forming the non-volatile memory device, wherein the plurality of protection structures (185a) extend between (e.g., extend through the interface between the buffer insulation layer 140/160 and the base insulation layer 170) the buffer insulation layer (140/160) (Kang, Fig. 8, ¶0031, ¶0037) and the base insulation layer (170) (Kang, Fig. 8, ¶0045) that is adjacent to the plurality of gate contact plugs (MCT) (Kang, Fig. 8, ¶0106), and wherein each protection structure (185a) (Kang, Fig. 8, ¶0104-¶0106) of the plurality of protection structures (185a) respectively is connected to one corresponding cut insulation layer (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) of the plurality of cut insulation layers.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact plugs as taught by Kang to have the non-volatile memory device, wherein the plurality of protection structures extend between the buffer insulation layer and the base insulation layer that is adjacent to the plurality of gate contact plugs, and wherein each protection structure of the plurality of protection structures respectively is connected to one corresponding cut insulation layer of the plurality of cut insulation layers, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claim 4, Cheng in view of Kang discloses the non-volatile memory device of claim 3. Further, Cheng does not specifically disclose that each protection structure of the plurality of protection structures comprises a step shape, and a portion of each protection structure of the plurality of protection structures between the base insulation layer and the buffer insulation layer corresponds to a step portion of the step shape.
However, Kang teaches forming the non-volatile memory device, wherein each protection structure (185a) (Kang, Fig. 8, ¶0104-¶0106) of the plurality of protection structures comprises a step shape (e.g., L shape including vertical portion and horizontal portion is interpreted as a step shape), and a portion of each protection structure of the plurality of protection structures between the base insulation layer (140/160) and the buffer insulation layer (170) corresponds to a step portion of the step shape.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact plugs surrounding by the plurality of protection layers as taught by Kang to have the non-volatile memory device, wherein each protection structure of the plurality of protection structures comprises a step shape, and a portion of each protection structure of the plurality of protection structures between the base insulation layer and the buffer insulation layer corresponds to a step portion of the step shape, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claims 5 and 6, Cheng in view of Kang discloses the non-volatile memory device of claim 1. Further, Cheng does not specifically disclose that each cut insulation layer of the plurality of cut insulation layers extends through the base insulation layer, extends between the common source line layer and the plurality of protection structures, and extends through the buffer insulation layer (as claimed in claim 5); wherein each of the plurality of cut insulation layers comprises a ring shape (as claimed in claim 6).
However, Kang teaches forming the non-volatile memory device, wherein each cut insulation layer (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) of the plurality of cut insulation layers extends through the base insulation layer (170) (Kang, Fig. 8, ¶0045), extends between the common source line layer (CSL) and the plurality of protection structures (185a), and extends through the buffer insulation layer (140/160) (Kang, Fig. 8, ¶0031, ¶0037); wherein each of the plurality of cut insulation layers (304a) comprises a ring shape (Kang, Figs. 2O, 8, ¶0076).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact plugs surrounding by the plurality of protection layers as taught by Kang to have the non-volatile memory device, wherein each cut insulation layer of the plurality of cut insulation layers extends through the base insulation layer, extends between the common source line layer and the plurality of protection structures, and extends through the buffer insulation layer (as claimed in claim 5); wherein each of the plurality of cut insulation layers comprises a ring shape (as claimed in claim 6), in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
With respect to claim 18, Cheng discloses a memory system (e.g., a system comprising processing units including processor and controller, and peripheral circuit of NAND memory device) (Cheng, Figs. 1A, 4A, ¶0005, ¶0044-¶0077) comprising:
a non-volatile memory device (NAND memory) comprising a peripheral circuit structure (416) (Cheng, Fig. 4A, ¶0064), wherein the peripheral circuit structure comprises a peripheral circuit (e.g., transistors 418), a first insulation structure (e.g., interconnect 420 including interlayer dielectric layer (ILD)) (Cheng, Fig. 4A, ¶0066) on the peripheral circuit (416), and a cell array structure (e.g., NAND memory strings 438) (Cheng, Fig. 4A, ¶0071-¶0073) on the peripheral circuit structure (416); and a memory controller (e.g., 412, processing units including processor and controller) (Cheng, Figs. 1A, 4A, ¶0050-¶0051, ¶0064) electrically connected to the non-volatile memory device,
wherein the cell array structure (438) comprises:
a base insulation layer (e.g., pad-out interconnect 450 including ILD) (Cheng, Fig. 4A, ¶0075);
a common source line layer (e.g., a semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the base insulation layer (450);
a buffer insulation layer (e.g., a pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the common source line layer (448);
a cell stack (e.g., memory stack 432) (Cheng, Fig. 4A, ¶0071-¶0074) on the buffer insulation layer (e.g., the pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448), wherein the cell stack (432) comprises a plurality of gate electrodes (434) and a plurality of insulation layers (436), and wherein the plurality of gate electrodes (434) have a nonlinear shape (e.g., a staircase shape) (Cheng, Fig. 4A,);
a plurality of cell channel structures (442/444) (Cheng, Fig. 4A, ¶0072-¶0073) that extend into the cell stack (432) and the buffer insulation layer (e.g., the pad oxide layer between the stack 432 and the semiconductor layer 448) and that are connected to the common source line layer (448); and
a second insulation structure (e.g., interconnect 430 including interlayer dielectric layer (ILD)) (Cheng, Fig. 4A, ¶0070) on the cell stack (432) and that is connected (e.g., through the bonding layer 422/426) to the first insulation structure (420).
Further, Cheng does not specifically disclose a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer; a plurality of cut insulation layers that extend into the base insulation layer, wherein the plurality of cut insulation layers are between the common source line layer and the plurality of protection structures, and wherein the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs.
However, Kang teaches forming a semiconductor memory device (Kang, Fig. 8, ¶0025-¶0078, ¶0095-¶0108) comprising word line contact region (WCTR) (Kang, Fig. 8, ¶0031) including a plurality of gate contact plugs (e.g., plugs MCT in the contact regions CTR1-CTR6) (Kang, Fig. 8, ¶0035, ¶0106) that extend into the cell stack (220) (Kang, Fig. 8, ¶0053-¶0061, ¶0104), wherein each gate contact plug (MCT) of the plurality of gate contact plugs is connected to one corresponding gate electrode (220) of the plurality of gate electrodes; a plurality of protection structures (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) between the plurality of gate contact plugs (MCT) and the base insulation layer (170) (Kang, Fig. 8, ¶0096); a plurality of cut insulation layers (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) that extend into the base insulation layer (170), wherein the plurality of cut insulation layers (304a) are between the common source line layer (CSL) and the plurality of protection structures (185a), and wherein the plurality of cut insulation layers (304a) at least partially surround the plurality of gate contact plugs (MCT).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng by forming a plurality of gate contact plugs as a plurality of word contact plugs of Kang in the word line contact region having a continuous step shape to have the non-volatile memory device comprising: a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer; a plurality of cut insulation layers that extend into the base insulation layer, wherein the plurality of cut insulation layers are between the common source line layer and the plurality of protection structures, and wherein the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claim 19, Cheng in view of Kang discloses the memory system of claim 18. Further, Cheng does not specifically disclose that each of the plurality of gate contact plugs extends through the base insulation layer, and each of the plurality of protection structures at least partially surrounds a portion of a corresponding gate contact plug of the plurality of gate contact plugs and extend between the buffer insulation layer and the base insulation layer that is adjacent to the plurality of gate contact plugs.
However, Kang teaches forming the non-volatile memory device, wherein each gate contact plug (MCT) (Kang, Fig. 8, ¶0106) of the plurality of gate contact plugs extends through the base insulation layer (170), and each protection structure (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) of the plurality of protection structures at least partially surrounds a portion of one corresponding gate contact plug (MCT) of the plurality of gate contact plugs, and wherein the plurality of protection structures (185a) extend between (e.g., extend through the interface between the buffer insulation layer 140/160 and the base insulation layer 170) the buffer insulation layer (140/160) (Kang, Fig. 8, ¶0031, ¶0037) and the base insulation layer (170) (Kang, Fig. 8, ¶0045) that is adjacent to the plurality of gate contact plugs (MCT) (Kang, Fig. 8, ¶0106),.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory system of Cheng/Kang by forming a plurality of gate contact plugs as taught by Kang to have the memory system, wherein each of the plurality of gate contact plugs extends through the base insulation layer, and each of the plurality of protection structures at least partially surrounds a portion of a corresponding gate contact plug of the plurality of gate contact plugs and extend between the buffer insulation layer and the base insulation layer that is adjacent to the plurality of gate contact plugs, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590) as applied to claim 1, and further in view of Liu et al. (US 2017/0117289, hereinafter Liu) and Lee et al. (US 2016/0071881, hereinafter Lee).
Regarding claim 7, Cheng in view of Kang discloses the non-volatile memory device of claim 1. Further, Cheng discloses the non-volatile memory device, wherein the plurality of cell channel structures (e.g., NAND structures 438) (Cheng, Fig. 4A, ¶0071-¶0073) extend into the cell stack (432), the buffer insulation layer (e.g., a pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448) (Cheng, Fig. 4A, ¶0074), and the common source line layer (448) (Cheng, Fig. 4A, ¶0074) is on a lower surface of the base insulation layer (450), but does not specifically disclose that (1) the plurality of cell channel structures extend into the base insulation layer, (2) the common source line layer is on inner surfaces of a plurality of grooves that extend from the lower surface of the base insulation layer and into the base insulation layer.
Regarding (1), Liu teaches forming a non-volatile memory including NAND-type, wherein the plurality of cell channel structures (e.g., NAND strings 502-508) (Liu, Fig. 5A, ¶0059-¶0062) extend into the cell stack (WLL0-WLL4 and DL0-DL7), the buffer insulation layer (DL0), and the base insulation layer (512), and including mechanical support structures (516), to provide reliable NAND memory structure (Liu, Fig. 5A, ¶0065-¶0066).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of NAND strings extending into the base insulation layer as taught by Liu to have the non-volatile memory device, wherein the plurality of cell channel structures extend into the base insulation layer, in order to provide reliable NAND memory structure (Liu, ¶0001, ¶0065-¶0066).
Regarding (2), Lee teaches forming a non-volatile memory device (Lee, Fig. 1A, ¶0020-¶0039) comprising the common source line layer (15A/15B) including a vertical source region (15B) on inner surfaces of a plurality of grooves that extend from a lower surface of the insulation layer (14) and into the insulation layer (14), to increase contact area with the channel layer (20), and to provide non-volatile memory device with improved characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Liu by forming the common source layer including a vertical source region in direct contact with the channel layer as taught by Lee to have the non-volatile memory device, wherein the common source line layer is on inner surfaces of a plurality of grooves that extend from the lower surface of the base insulation layer and into the base insulation layer, in order to increase contact area with the channel layer, and to provide non-volatile memory device with improved characteristics (Lee, ¶0020, ¶0025-¶0030).
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590) as applied to claim 1, and further in view of Lee (US 2016/0071881).
Regarding claim 8, Cheng in view of Kang discloses the non-volatile memory device of claim 1. Further, Cheng does not specifically disclose that each of the common source line layer and the plurality of protection structures comprises a same material and a same thickness.
However, Lee teaches forming a non-volatile memory device (Lee, Fig. 1A, ¶0020-¶0039) comprising the common source line layer (15A/15B) including a vertical source region (15B) on inner surfaces of a plurality of grooves that extend from a lower surface of the insulation layer (14) and into the insulation layer (14), to increase contact area with the channel layer (20), and to provide non-volatile memory device with improved characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming the common source layer including a vertical source region of Lee that is in direct contact with the channel layer as a protection structure to have the non-volatile memory device, wherein each of the common source line layer and the plurality of protection structures comprises a same material and a same thickness, in order to increase contact area with the channel layer, and to provide non-volatile memory device with improved characteristics (Lee, ¶0020, ¶0025-¶0030).
Regarding claim 20, Cheng in view of Kang discloses the memory system of claim 18. Further, Cheng does not specifically disclose that each of the common source line layer and each of the plurality of protection structures comprises a same material and a same thickness.
However, Lee teaches forming a non-volatile memory device (Lee, Fig. 1A, ¶0020-¶0039) comprising the common source line layer (15A/15B) including a vertical source region (15B) on inner surfaces of a plurality of grooves that extend from a lower surface of the insulation layer (14) and into the insulation layer (14), to increase contact area with the channel layer (20), and to provide non-volatile memory device with improved characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory system of Cheng/Kang by forming the common source layer including a vertical source region of Lee that is in direct contact with the channel layer as a protection structure to have the memory system, wherein each of the common source line layer and each of the plurality of protection structures comprises a same material and a same thickness, in order to increase contact area with the channel layer, and to provide non-volatile memory device with improved characteristics (Lee, ¶0020, ¶0025-¶0030).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590) as applied to claim 1, and further in view of Liu (US 2017/0117289) and Lee et al. (US 2022/0093635, hereinafter Lee’635).
Regarding claim 9, Cheng in view of Kang discloses the non-volatile memory device of claim 1. Further, Cheng discloses the non-volatile memory device, wherein the cell array structure further comprises a plurality of dummy channel structures (e.g., NAND strings 438 in the peripheral region and not connected to the peripheral circuit of the NAND structure) (Cheng, Fig. 4A, ¶0071-¶0073) that extend into the cell stack (432), but does not specifically disclose that (1) the plurality of dummy channel structures and the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs, each cut insulation layer of the plurality of cut insulation layers is between one corresponding gate contact plug of the plurality of gate contact plugs and one corresponding dummy channel structure of the plurality of dummy channel structures, (2) each dummy channel structure of the plurality of dummy channel structures extends through the base insulation layer, and (3) the common source line layer at least partially surrounds a portion of each gate contact plug of the plurality of gate contact plugs that extends through the base insulation layer.
Regarding (1), Kang teaches forming a semiconductor memory device (Kang, Fig. 8, ¶0025-¶0078, ¶0095-¶0108) comprising word line contact region (WCTR) (Kang, Fig. 8, ¶0031) including a plurality of gate contact plugs (e.g., plugs MCT in the contact regions CTR1-CTR6) (Kang, Fig. 8, ¶0035, ¶0106) that extend into the cell stack (220) (Kang, Fig. 8, ¶0053-¶0061, ¶0104), wherein each gate contact plug (MCT) of the plurality of gate contact plugs is connected to one corresponding gate electrode (220) of the plurality of gate electrodes; a plurality of protection structures (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) between the plurality of gate contact plugs (MCT) and the base insulation layer (170) (Kang, Fig. 8, ¶0096); a plurality of cut insulation layers (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) that extend into the base insulation layer (170), wherein the plurality of dummy channel structures (200D) (Kang, Fig. 8, ¶0041) and the plurality of cut insulation layers (304a) at least partially surround the plurality of gate contact plugs (MCT), each cut insulation layer (304a) of the plurality of cut insulation layers is between one corresponding gate contact plug (MCT) of the plurality of gate contact plugs and one corresponding dummy channel structure (200D) of the plurality of dummy channel structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact plugs as a plurality of word contact plugs of Kang in the word line contact region having a continuous step shape, wherein the plurality of gate contact plugs are surrounded by the dummy channel structures to have the non-volatile memory device, wherein the plurality of dummy channel structures and the plurality of cut insulation layers at least partially surround the plurality of gate contact plugs, each cut insulation layer of the plurality of cut insulation layers is between one corresponding gate contact plug of the plurality of gate contact plugs and one corresponding dummy channel structure of the plurality of dummy channel structures, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding (2), Liu teaches forming a non-volatile memory including NAND-type, wherein the plurality of cell channel structures (e.g., NAND strings 502-508) (Liu, Fig. 5A, ¶0059-¶0062) extend into the cell stack (WLL0-WLL4 and DL0-DL7), the buffer insulation layer (DL0), and the base insulation layer (512), and including mechanical support structures (516), to provide reliable NAND memory structure (Liu, Fig. 5A, ¶0065-¶0066).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of dummy channel structures as NAND strings of Liu that extend into the base insulation layer to have the non-volatile memory device, wherein each dummy channel structure of the plurality of dummy channel structures extends through the base insulation layer, in order to provide reliable NAND memory structure (Liu, ¶0001, ¶0065-¶0066).
Regarding (3), Lee’635 teaches forming a memory device (Lee’635, Figs. 4A-4C, ¶0046-¶0078) comprising the cell stacked structure connected to the common source line (105) (Lee’635, Figs. 4A-4C, ¶0072) and the contact region including a plurality of gate contact structures (GCT1-GCT4) (Lee’635, Figs. 4A-4C, ¶0053-¶0060, ¶0066, ¶0076), whereon portions of sidewalls of the plurality of gate contact structures (GCT1-GCT4) are surrounded by the common source line layer (105) and the plurality of gate contact structures (GCT1-GCT4) extend through the base insulation layer (101) (Lee’635, Figs. 4A-4C, ¶0065-¶0066, ¶0072, ¶0076).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang by forming a plurality of gate contact structures penetration the common source line layer as taught by Lee’635 to have the non-volatile memory device, wherein the common source line layer at least partially surrounds a portion of each gate contact plug of the plurality of gate contact plugs that extends through the base insulation layer, in order to provide memory device with improved degree of integration (Lee’635, ¶0004, ¶0005, ¶0032, ¶0066, ¶0072, ¶0076).
Claims 10, 12-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590), Song et al. (KR 20200022147 A, hereinafter Song), and Oike (US 2019/0371811).
With respect to claim 10, Cheng discloses a non-volatile memory device (e.g., NAND memory device) (Cheng, Fig. 4A, ¶0005, ¶0044-¶0077) comprising:
a peripheral circuit structure (412-416) (Cheng, Fig. 4A, ¶0064) comprising a peripheral circuit (e.g., transistors 418) and a first insulation structure (e.g., interconnect 420 including interlayer dielectric layer (ILD)) (Cheng, Fig. 4A, ¶0066) on the peripheral circuit (412-416); and
a cell array structure (e.g., NAND memory strings 438) (Cheng, Fig. 4A, ¶0071-¶0073) on the peripheral circuit structure (412-416), wherein the cell array structure (438) comprises:
a base insulation layer (e.g., pad-out interconnect 450 including ILD) (Cheng, Fig. 4A, ¶0075);
a common source line layer (e.g., a semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the base insulation layer (450);
a buffer insulation layer (e.g., a pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448) (Cheng, Fig. 4A, ¶0074) on the common source line layer (448);
a cell stack (e.g., memory stack 432) (Cheng, Fig. 4A, ¶0071-¶0074) on the buffer insulation layer (e.g., the pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448), wherein the cell stack (432) comprises a plurality of gate electrodes (434) and a plurality of insulation layers (436), and wherein the plurality of gate electrodes (434) have a nonlinear shape (e.g., a staircase shape) (Cheng, Fig. 4A,);
a plurality of cell channel structures (442/444) (Cheng, Fig. 4A, ¶0072-¶0073) that extend into the cell stack (432) and the buffer insulation layer (e.g., the pad oxide layer between the stack 432 and the semiconductor layer 448) and that are connected to the common source line layer (448);
an insulation layer (e.g., one of the ILD layers of the interconnect 430) on the common source line layer (448) and the cell stack (432);
a plurality of through contact plugs (e.g., one or more contacts 454 connected to the peripheral circuits 412-416) (Cheng, Fig. 4A, ¶0077) that extend into the insulation layer (e.g., ILD of the interconnect 430) and are connected to the peripheral circuit (412-416);
a plurality of peripheral connection pads (e.g., portions of the one or more contacts 454 in the interconnect layer 450) (Cheng, Fig. 4A, ¶0077) that are connected to the plurality of through contact plugs and within the base insulation layer (e.g., pad-out interconnect 450 including ILD) (Cheng, Fig. 4A, ¶0075); and
a second insulation structure (e.g., interconnect 430 including interlayer dielectric layers (ILD)) (Cheng, Fig. 4A, ¶0070) that is on the cell stack (432) and the insulation layer (e.g., one of the ILD layers of the interconnect 430) and connected (e.g., through the bonding layer 422/426) to the first insulation structure (420).
Further, Cheng does not specifically disclose (1) a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of first protection structures, wherein each first protection structure of the plurality of first protection structures is between one corresponding gate contact plug of the plurality of gate contact plugs and the base insulation layer; a plurality of first cut insulation layers that extend into at least a portion of the base insulation layer, wherein each first cut insulation layer of the plurality of first cut insulation layers is between the common source line layer and one corresponding first protection structure of the plurality of first protection structures to at least partially surround one corresponding gate contact plug of the plurality of gate contact plugs; (2) a plurality of dummy channel structures that extend into the cell stack and are connected to the common source line layer, wherein each dummy channel structure of the plurality of dummy channel structures at least partially surrounds one corresponding gate contact plug of the plurality of gate contact plugs; (3) a charge insulation layer; (4) a plurality of second protection structures, wherein each second protection structure of the plurality of second protection structures is between one corresponding peripheral connection pad of the plurality of peripheral connection pads and the base insulation layer; a second cut insulation layer that extends through at least a portion of the base insulation layer, wherein the second cut insulation layer is between the common source line layer and the plurality of second protection structures to at least partially surround at least one of the plurality of through contact plugs.
Regarding (1) and (2), Kang teaches forming a semiconductor memory device (Kang, Fig. 8, ¶0025-¶0078, ¶0095-¶0108) comprising word line contact region (WCTR) (Kang, Fig. 8, ¶0031) including a plurality of gate contact plugs (e.g., plugs MCT in the contact regions CTR1-CTR6) (Kang, Fig. 8, ¶0035, ¶0106) that extend into the cell stack (220) (Kang, Fig. 8, ¶0053-¶0061, ¶0104), wherein each gate contact plug (MCT) of the plurality of gate contact plugs is connected to one corresponding gate electrode (220) of the plurality of gate electrodes; a plurality of protection structures (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) between the plurality of gate contact plugs (MCT) and the base insulation layer (170) (Kang, Fig. 8, ¶0096); a plurality of cut insulation layers (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) that extend into the base insulation layer (170), wherein the plurality of cut insulation layers (304a) are between the common source line layer (CSL) and the plurality of protection structures (185a), and wherein the plurality of cut insulation layers (304a) at least partially surround the plurality of gate contact plugs (MCT).
Further, Kang teaches a plurality of dummy channel structures (200D) (Kang, Fig. 8, ¶0041) that extend into the cell stack (220) and are connected to the substrate layer (100), wherein each dummy channel structure (200D) of the plurality of dummy channel structures at least partially surrounds one corresponding gate contact plug (MCT) of the plurality of gate contact plugs.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng by forming a plurality of gate contact plugs as a plurality of word contact plugs of Kang in the word line contact region having a continuous step shape, wherein the plurality of gate contact plugs are surrounded by the dummy channel structures to have the non-volatile memory device comprising: a plurality of gate contact plugs that extend into the cell stack, wherein each gate contact plug of the plurality of gate contact plugs is connected to one corresponding gate electrode of the plurality of gate electrodes; a plurality of first protection structures, wherein each first protection structure of the plurality of first protection structures is between one corresponding gate contact plug of the plurality of gate contact plugs and the base insulation layer; a plurality of first cut insulation layers that extend into at least a portion of the base insulation layer, wherein each first cut insulation layer of the plurality of first cut insulation layers is between the common source line layer and one corresponding first protection structure of the plurality of first protection structures to at least partially surround one corresponding gate contact plug of the plurality of gate contact plugs; a plurality of dummy channel structures that extend into the cell stack and are connected to the common source line layer, wherein each dummy channel structure of the plurality of dummy channel structures at least partially surrounds one corresponding gate contact plug of the plurality of gate contact plugs, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding (3), Song teaches forming a semiconductor device (Song, Fig. 2a, pp. 1-4) comprising a charge insulation layer (155) including a low dielectric constant material, to reduce parasitic capacitance between the contacts.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng by forming a charge insulation layer including a low dielectric constant material as taught by Song to have the non-volatile memory device comprising: a charge insulation layer, in order to reduce parasitic capacitance between the contacts, and to provide a semiconductor device with increased degree of integration (Song, pp. 1, 4).
Regarding (4), Oike teaches forming a semiconductor nonvolatile memory device (Oike, Figs. 13-14, ¶0003, ¶0032, ¶0080-¶0082, ¶0138, ¶0152-¶0167, ¶0183-¶0198) comprising a plurality of contacts (C4) and a plurality of protection structures (e.g., spacers SP), wherein each protection structure (SP) is between one corresponding peripheral connection pad (48) and the base insulation layer (e.g., insulation layer under source line 21B and on the substrate 20); a cut insulation layer (e.g., slits SLTs) that extends through at least a portion of the base insulation layer, wherein the cut insulation layer (SLTs) is between the common source line layer (e.g., 21B) and the plurality of protection structures (SP) (Oike, Fig. 13) to at least partially surround at least one of the plurality of through contact plugs (C4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng by forming a plurality of through contact plugs as a plurality of peripheral contact plugs surrounded by the insulating spacers and the vertical slits as taught by Oike to have the non-volatile memory device comprising: a plurality of second protection structures, wherein each second protection structure of the plurality of second protection structures is between one corresponding peripheral connection pad of the plurality of peripheral connection pads and the base insulation layer; a second cut insulation layer that extends through at least a portion of the base insulation layer, wherein the second cut insulation layer is between the common source line layer and the plurality of second protection structures to at least partially surround at least one of the plurality of through contact plugs, in order to provide a nonvolatile memory device having insulating slits to prevent a noise component of the source line to improve reliability of data stored in memory cells (Oike, ¶0003, ¶0183-¶0184, ¶0194-¶0198).
Regarding claim 12, Cheng in view of Kang, Song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng does not specifically disclose that each first cut insulation layer of the plurality of first cut insulation layers comprises a ring shape and is between one corresponding gate contact plug of the plurality of gate contact plugs and one corresponding dummy channel structure of the plurality of dummy channel structures.
However, Kang teaches forming the non-volatile memory device, wherein each of the plurality of cut insulation layers (304a) comprises a ring shape (Kang, Figs. 2O, 8, ¶0076) and is between one corresponding gate contact plug (MCT) of the plurality of gate contact plugs and one corresponding dummy channel structure (200D) of the plurality of dummy channel structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming a plurality of gate contact plugs surrounding by the plurality of protection layers and dummy channel structures as taught by Kang to have the non-volatile memory device, wherein each first cut insulation layer of the plurality of first cut insulation layers comprises a ring shape and is between one corresponding gate contact plug of the plurality of gate contact plugs and one corresponding dummy channel structure of the plurality of dummy channel structures, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claims 13 and 14, Cheng in view of Kang, Song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng does not specifically disclose the non-volatile memory device, further comprising a plurality of the second cut insulation layers , and each of the plurality of second cut insulation layers has a ring shape that at least partially surrounds each of the plurality of second protection structures connected to the plurality of peripheral connection pads (as claimed in claim 13); wherein the second cut insulation layer at least partially surrounds the plurality of second protection structures (as claimed in claim 14).
However, Oike teaches forming a semiconductor nonvolatile memory device (Oike, Figs. 13-14, ¶0003, ¶0032, ¶0080-¶0082, ¶0138, ¶0152-¶0167, ¶0183-¶0198) comprising a plurality of contacts (C4) and a plurality of protection structures (e.g., spacers SP), and a plurality of the cut insulation layers (e.g., slits SLTs), wherein each of the plurality of the cut insulation layers (SLTs) surrounds each of the plurality of protection structures (SP) (Oike, Fig. 13), and the cut insulation layer (SLTs) at least partially surrounds the plurality of second protection structures (SP), and wherein the contact (C4) has columnar shape (Oike, Fig. 14, ¶0165). Further, the slits (SLTs) form a ring shape to surround the plurality of contact plugs (C4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming a plurality of through contact plugs as a plurality of peripheral contact plugs surrounded by the insulating spacers and the vertical slits as taught by Oike, wherein the silts form a ring shape to have the non-volatile memory device, further comprising a plurality of the second cut insulation layers , and each of the plurality of second cut insulation layers has a ring shape that at least partially surrounds each of the plurality of second protection structures connected to the plurality of peripheral connection pads (as claimed in claim 13); wherein the second cut insulation layer at least partially surrounds the plurality of second protection structures (as claimed in claim 14), in order to provide a nonvolatile memory device having insulating slits to prevent a noise component of the source line to improve reliability of data stored in memory cells (Oike, ¶0003, ¶0183-¶0184, ¶0194-¶0198).
Regarding claim 15, Cheng in view of Kang, Song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng does not specifically disclose that each of the plurality of gate contact plugs extends through the base insulation layer, and each of the plurality of first protection structures comprises a step shape that surrounds a portion of each of the plurality of gate contact plugs and that extends between the buffer insulation layer and the base insulation layer.
However, Kang teaches forming the non-volatile memory device, wherein each gate contact plug (MCT) (Kang, Fig. 8, ¶0106) of the plurality of gate contact plugs extends through the base insulation layer (170), and each protection structure (e.g., spacers 185a) (Kang, Fig. 8, ¶0104-¶0106) of the plurality of protection structures comprises a step shape (e.g., L shape including vertical portion and horizontal portion is interpreted as a step shape) that surrounds a portion of each of the plurality of gate contact plugs (MCT) and that extends between the buffer insulation layer and the base insulation layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming a plurality of gate contact plugs as taught by Kang to have the non-volatile memory device, wherein each of the plurality of gate contact plugs extends through the base insulation layer, and each of the plurality of first protection structures comprises a step shape that surrounds a portion of each of the plurality of gate contact plugs and that extends between the buffer insulation layer and the base insulation layer, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Regarding claim 17, Cheng in view of Kang, Song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng does not specifically disclose that each of the plurality of first cut insulation layers extends through at least a portion of the base insulation layer, extends between the common source line layer and the plurality of first protection structures, and extends through the buffer insulation layer in a vertical direction.
However, Kang teaches that each of the plurality of cut insulation layers (304a) (Kang, Fig. 8, ¶0096, ¶0105-¶0106) extends through at least a portion of the base insulation layer (140/160), extends between the common source line layer (CSL) and the plurality of first protection structures (185a), and extends through the buffer insulation layer (140160) in a vertical direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming a plurality of gate contact plugs surrounded by the plurality of cut insulation layers as taught by Kang to have the non-volatile memory device, wherein each of the plurality of first cut insulation layers extends through at least a portion of the base insulation layer, extends between the common source line layer and the plurality of first protection structures, and extends through the buffer insulation layer in a vertical direction, in order to provide integrated circuit device including a memory device having improved integration and excellent electrical characteristics (Kang, ¶0003, ¶0105-¶0106).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590), Song (KR 20200022147 A), and Oike (US 2019/0371811) as applied to claim 10, and further in view of Lee (US 2016/0071881).
Regarding claim 11, Cheng in view of Kang, Song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng does not specifically disclose that each of the common source line layer and the plurality of first protection structures comprises a same material and a same thickness.
However, Lee teaches forming a non-volatile memory device (Lee, Fig. 1A, ¶0020-¶0039) comprising the common source line layer (15A/15B) including a vertical source region (15B) on inner surfaces of a plurality of grooves that extend from a lower surface of the insulation layer (14) and into the insulation layer (14), to increase contact area with the channel layer (20), and to provide non-volatile memory device with improved characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming the common source layer including a vertical source region of Lee that is in direct contact with the channel layer as a first protection structure to have the non-volatile memory device, wherein each of the common source line layer and the plurality of first protection structures comprises a same material and a same thickness, in order to increase contact area with the channel layer, and to provide non-volatile memory device with improved characteristics (Lee, ¶0020, ¶0025-¶0030).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0350320 to Cheng in view of Kang (US 2017/0358590), Song (KR 20200022147 A), and Oike (US 2019/0371811) as applied to claim 10, and further in view of Liu (US 2017/0117289) and Lee (US 2016/0071881).
Regarding claim 16, Cheng in view of Kang, song, and Oike discloses the non-volatile memory device of claim 10. Further, Cheng discloses the non-volatile memory device, wherein each of the plurality of cell channel structures (e.g., NAND structures 438) (Cheng, Fig. 4A, ¶0071-¶0073) and each of the plurality of dummy channel structures (e.g., NAND strings 438 above the peripheral processor region 412) extend into the cell stack (432), the buffer insulation layer (e.g., a pad oxide layer including silicon oxide layer between the stack 432 and the semiconductor layer 448) (Cheng, Fig. 4A, ¶0074), and the common source line layer (448) (Cheng, Fig. 4A, ¶0074) is on a lower surface of the base insulation layer (450), but does not specifically disclose that (1) each of the plurality of cell channel structures and each of the plurality of dummy channel structures extend into the base insulation layer, (2) the common source line layer is on inner surfaces of a plurality of grooves that extend from the lower surface of the base insulation layer and into the base insulation layer.
Regarding (1), Liu teaches forming a non-volatile memory including NAND-type, wherein the plurality of cell channel structures (e.g., NAND strings 502-508) (Liu, Fig. 5A, ¶0059-¶0062) extend into the cell stack (WLL0-WLL4 and DL0-DL7), the buffer insulation layer (DL0), and the base insulation layer (512), and including mechanical support structures (516), to provide reliable NAND memory structure (Liu, Fig. 5A, ¶0065-¶0066).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike by forming a plurality of NAND strings extending into the base insulation layer as taught by Liu to have the non-volatile memory device, wherein each of the plurality of cell channel structures and each of the plurality of dummy channel structures extend into the base insulation layer, in order to provide reliable NAND memory structure (Liu, ¶0001, ¶0065-¶0066).
Regarding (2), Lee teaches forming a non-volatile memory device (Lee, Fig. 1A, ¶0020-¶0039) comprising the common source line layer (15A/15B) including a vertical source region (15B) on inner surfaces of a plurality of grooves that extend from a lower surface of the insulation layer (14) and into the insulation layer (14), to increase contact area with the channel layer (20), and to provide non-volatile memory device with improved characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the non-volatile memory device of Cheng/Kang/Song/Oike/ Liu by forming the common source layer including a vertical source region in direct contact with the channel layer as taught by Lee to have the non-volatile memory device, wherein the common source line layer is on inner surfaces of a plurality of grooves that extend from the lower surface of the base insulation layer and into the base insulation layer, in order to increase contact area with the channel layer, and to provide non-volatile memory device with improved characteristics (Lee, ¶0020, ¶0025-¶0030).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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