DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites “a second sub-bonding layer on the second surface of the second semiconductor substrate” and “the first sub-bonding layer and the second sub-bonding layer are …between the first stack and the second stack”, and it is unclear on which surface of the second semiconductor substrate “a second sub-bonding layer” is arranged because claim 11 (upon which claim 14 depends) recites “a second semiconductor substrate comprising a first surface that faces the first surface of the first semiconductor substrate”. Thus, “a second sub-bonding layer” has to be formed on the first surface of the second semiconductor substrate in order to arrange “the first sub-bonding layer and the second sub-bonding layer …between the first stack and the second stack” (as required by claim 14).
Thus, for the compact persecution, the limitations of claim 14 “a second sub-bonding layer on the second surface of the second semiconductor substrate” are interpreted as “a second sub-bonding layer on the first surface of the second semiconductor substrate”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0238590 to Hiramatsu et al. (hereinafter Hiramatsu).
With respect to claim 1, Hiramatsu discloses an image sensor (see the annotated Fig. 6 below) (Hiramatsu, Figs. 2-3, 6, ¶0140-¶0185) comprising:
a first stack (100) (Hiramatsu, Fig. 6, ¶0140, ¶0158-¶0159) comprising:
a first semiconductor substrate (100S) comprising a first surface (e.g., a top surface in Fig. 6) and a second surface (e.g., a bottom surface in Fig. 6) opposite to the first surface,
a photoelectric conversion region (PD) (Hiramatsu, Fig. 6, ¶0150, ¶0152, ¶0159) in the first semiconductor substrate (100S), and
a floating diffusion region (FD) (Hiramatsu, Fig. 6, ¶0150-¶0151, ¶0161) in the first semiconductor substrate (100S), the floating diffusion region (FD) being configured to store charges transferred from the photoelectric conversion region (PD);
a second stack (200) comprising:
a second semiconductor substrate (200S) (Hiramatsu, Fig. 6, ¶0140, ¶0158, ¶0177-¶0178) comprising a first surface (e.g., a top surface in Fig. 6) and a second surface (e.g., a bottom surface in Fig. 6) opposite the first surface, and
a transmission gate (TG/TVG) (Hiramatsu, Fig. 6, ¶0152, ¶0163-¶0164) penetrating through the second semiconductor substrate (200S) and extending into the first stack (100); and
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an insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) between the first stack (100S) and the second stack (200).
Regarding claim 2, Hiramatsu discloses the image sensor of claim 1. Further, Hiramatsu discloses the image sensor, wherein the insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) covers at least a portion of a sidewall of the transmission gate (TG/TVG).
Regarding claim 3, Hiramatsu discloses the image sensor of claim 2. Further, Hiramatsu discloses the image sensor, wherein the insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) is disposed between the first surface (e.g., a top surface in Fig. 6) of the first semiconductor substrate (100S) and the second surface (e.g., a bottom surface in Fig. 6) of the second semiconductor substrate (200S).
Regarding claim 4, Hiramatsu discloses the image sensor of claim 1. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises a filling insulation layer (212) (Hiramatsu, Fig. 6, ¶0188-¶0189) in an opening penetrating through the second semiconductor substrate (200S), and wherein the transmission gate (TG/TGV) penetrates through the filling insulation layer (212) and the insulation layer (123/124) and extends in a vertical direction (e.g., a direction perpendicular to main surfaces of the first substrate 100S and the second substrate 200S) (Hiramatsu, Fig. 6, ¶0158).
Regarding claim 5, Hiramatsu discloses the image sensor of claim 1. Further, Hiramatsu discloses the image sensor, wherein the insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) comprises: a first sub-bonding layer (123) attached on the first surface (e.g., the top surface in Fig. 6) of the first semiconductor substrate (100S); and a second sub-bonding layer (124) attached on the second surface (e.g., the bottom surface in Fig. 6) of the second semiconductor substrate (200S), and wherein the first sub-bonding layer and the second sub-bonding layer are arranged throughout an area between the first stack (100) and the second stack (200).
Regarding claim 6, Hiramatsu discloses the image sensor of claim 5. Further, Hiramatsu discloses the image sensor, wherein the first sub-bonding layer (e.g., 123, formed of silicon oxide) (Hiramatsu, Fig. 6, ¶0184) or the second sub-bonding layer (124) comprises at least one (e.g., silicon oxide) of silicon oxide or silicon carbon nitride.
Regarding claim 7, Hiramatsu discloses the image sensor of claim 1. Further, Hiramatsu discloses the image sensor, wherein the first stack (100) further comprises a pixel device isolation layer (117) (Hiramatsu, Fig. 6, ¶0160, ¶0165) in a pixel trench penetrating through the first semiconductor substrate (100S), wherein the pixel device isolation layer (117) comprises a plurality of pixels (541) (Hiramatsu, Fig. 6, ¶0158-¶0162) in the first stack, and wherein the photoelectric conversion region (PD) and the floating diffusion region (FD) are provided in at least one pixel (541) of the plurality of pixels.
Regarding claim 8, Hiramatsu discloses the image sensor of claim 7. Further, Hiramatsu discloses the image sensor, wherein the first stack further comprises a conductive layer (e.g., pad portion 120) (Hiramatsu, Fig. 6, ¶0160, ¶0170-¶0177) vertically overlapping at least a portion of the pixel device isolation layer (117) at a position adjacent to the first surface of the first semiconductor substrate (100S), and wherein the floating diffusion region (FD) surrounds the conductive layer (120) in a plan view (Hiramatsu, Fig. 7B, ¶0176).
Regarding claim 9, Hiramatsu discloses the image sensor of claim 8. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises a contact (120E) (Hiramatsu, Fig. 6, ¶0161, ¶0181-¶0182, ¶0188, ¶0190) that penetrates through the second semiconductor substrate (200S) and that is connected to the conductive layer (120), and wherein a portion of a sidewall of the contact (120E) is covered by the insulation layer (123/124).
Regarding claim 10, Hiramatsu discloses the image sensor of claim 1. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises a pixel gate (e.g., pixel circuit 210 including a gate electrode of the amplification transistor AMP) (Hiramatsu, Fig. 6, ¶0172, ¶0174) on the first surface (e.g., the top surface) of the second semiconductor substrate (200S), wherein the image sensor further comprises a third stack (300) (Hiramatsu, Fig. 6, ¶0140, ¶0218) attached to the second stack (200), and wherein the third stack (300) comprises a logic transistor (Hiramatsu, Fig. 6, ¶0504) configured to provide signals to the pixel gate (e.g., through contact 301 and wiring 200T) (Hiramatsu, Fig. 6, ¶0191-¶0192, ¶0214-¶0215) and the transmission gate (TG/TGV).
With respect to claim 11, Hiramatsu discloses an image sensor (see the annotated Fig. 6 above) (Hiramatsu, Figs. 2-3, 6, ¶0140-¶0185) comprising:
a first stack (100) (Hiramatsu, Fig. 6, ¶0140, ¶0158-¶0159) comprising:
a first semiconductor substrate (100S) comprising a first surface (e.g., a bottom surface in the flipped Fig. 6) and a second surface (e.g., a top surface in the flipped Fig. 6) opposite to the first surface,
a photoelectric conversion region (PD) (Hiramatsu, Fig. 6, ¶0150, ¶0152, ¶0159) in the first semiconductor substrate (100S), and
a floating diffusion region (FD) (Hiramatsu, Fig. 6, ¶0150-¶0151, ¶0161) in the first semiconductor substrate (100S), the floating diffusion region (FD) being configured to store charges transferred from the photoelectric conversion region (PD);
a second stack (200) (Hiramatsu, Fig. 6, ¶0140, ¶0158, ¶0177-¶0178) comprising:
a second semiconductor substrate (200S) comprising a first surface (e.g., a top surface of 200S in the flipped Fig. 6) that faces the first surface (e.g., the bottom surface of 100S in the flipped Fig. 6) of the first semiconductor substrate (100S), and a second surface (e.g., a bottom surface of 200S in the flipped Fig. 6) opposite the first surface,
a pixel gate (e.g., pixel circuit 210 including a gate electrode of the amplification transistor AMP) (Hiramatsu, Fig. 6, ¶0172, ¶0174) on the first surface of the second semiconductor substrate (200S), and
a transmission gate (TG/TVG) (Hiramatsu, Fig. 6, ¶0152, ¶0163-¶0164) comprising a first end portion (TGa) disposed at a level higher than that of the first surface (e.g., the bottom surface of 100S in the flipped Fig. 6) of the first semiconductor substrate (100S) and a second end portion (TGV) disposed at a level lower than that of the first surface (e.g., the top surface of 200S in the flipped Fig. 6) of the second semiconductor substrate (200S); and
an insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) between the first stack (100S) and the second stack (200),
wherein a portion of a sidewall of the transmission gate (TG/TGV) is surrounded by the insulation layer (123/124).
Regarding claim 12, Hiramatsu discloses the image sensor of claim 11. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises a filling insulation layer (212) (Hiramatsu, Fig. 6, ¶0188-¶0189) in an opening penetrating through the second semiconductor substrate (200S), and wherein the transmission gate (Tg/TGV) penetrates through the filling insulation layer (212) and the insulation layer (123/124) and extends in a vertical direction.
Regarding claim 13, Hiramatsu discloses the image sensor of claim 12. Further, Hiramatsu discloses the image sensor, wherein the second semiconductor substrate (200S) (Hiramatsu, Fig. 6, ¶0140, ¶0158, ¶0177-¶0178) has a first thickness in the vertical direction, and wherein the transmission gate (TG/TGV) (Hiramatsu, Fig. 6, ¶0152, ¶0163-¶0164) has a second thickness greater than the first thickness in the vertical direction.
Regarding claim 14, Hiramatsu discloses the image sensor of claim 12. Further, Hiramatsu discloses the image sensor, wherein the insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) comprises: a first sub-bonding layer (123) on the first surface (e.g., the bottom surface of 100S in the flipped Fig. 6) of the first semiconductor substrate (100S); and a second sub-bonding layer (124) attached on the first surface (e.g., the top surface of 200S in flipped Fig. 6) of the second semiconductor substrate (200S), and wherein the first sub-bonding layer (123) and the second sub-bonding layer (124) are arranged throughout an area between the first stack (100S) and the second stack (200S).
Regarding claim 15, Hiramatsu discloses the image sensor of claim 14. Further, Hiramatsu discloses the image sensor, wherein the first sub-bonding layer (e.g., 123, formed of silicon oxide) (Hiramatsu, Fig. 6, ¶0184) or the second sub-bonding layer (124) comprises at least one (e.g., silicon oxide) of silicon oxide or silicon carbon nitride.
Regarding claim 16, Hiramatsu discloses the image sensor of claim 12. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises a contact (120E) (Hiramatsu, Fig. 6, ¶0161, ¶0181-¶0182, ¶0188, ¶0190) that penetrates through the filling insulation layer (212) and the insulation layer (123/124) and that is electrically connected to the floating diffusion region (FD) (Hiramatsu, Fig. 6, ¶0161).
Regarding claim 17, Hiramatsu discloses the image sensor of claim 16. Further, Hiramatsu discloses the image sensor, further comprises a third stack (300) (Hiramatsu, Fig. 6, ¶0140, ¶0218) attached to the second stack (200), and wherein the third stack (300) comprises a logic transistor (Hiramatsu, Fig. 6, ¶0504) configured to provide signals to the pixel gate (e.g., through contact 301 and wiring 200T) (Hiramatsu, Fig. 6, ¶0191-¶0192, ¶0214-¶0215) and the transmission gate (TG/TGV).
With respect to claim 18, Hiramatsu discloses an image sensor (see the annotated Fig. 6 above) (Hiramatsu, Figs. 2-3, 6, ¶0140-¶0185) comprising:
a first stack (100) (Hiramatsu, Fig. 6, ¶0140, ¶0158-¶0159) comprising:
a first semiconductor substrate (100S) comprising a first surface (e.g., a bottom surface in the flipped Fig. 6) and a second surface (e.g., a top surface in the flipped Fig. 6) opposite to the first surface,
a photoelectric conversion region (PD) (Hiramatsu, Fig. 6, ¶0150, ¶0152, ¶0159) in the first semiconductor substrate (100S), and
a floating diffusion region (FD) (Hiramatsu, Fig. 6, ¶0150-¶0151, ¶0161) in the first semiconductor substrate (100S), the floating diffusion region (FD) being configured to store charges transferred from the photoelectric conversion region (PD);
a second stack (200) (Hiramatsu, Fig. 6, ¶0140, ¶0158, ¶0177-¶0178) comprising:
a second semiconductor substrate (200S) comprising a first surface (e.g., a top surface of 200S in the flipped Fig. 6) that faces the first surface (e.g., the bottom surface of 100S in the flipped Fig. 6) of the first semiconductor substrate (100S), and a second surface (e.g., a bottom surface of 200S in the flipped Fig. 6) opposite the first surface,
a pixel gate (e.g., pixel circuit 210 including a gate electrode of the amplification transistor AMP) (Hiramatsu, Fig. 6, ¶0172, ¶0174) on the first surface of the second semiconductor substrate (200S), and
a transmission gate (TG/TVG) (Hiramatsu, Fig. 6, ¶0152, ¶0163-¶0164) comprising a first end portion (TGa) disposed at a level higher than that of the first surface (e.g., the bottom surface of 100S in the flipped Fig. 6) of the first semiconductor substrate (100S) and a second end portion (TGV) disposed at a level lower than that of the first surface (e.g., the top surface of 200S in the flipped Fig. 6) of the second semiconductor substrate (200S); and
a first insulation layer (123/124) (Hiramatsu, Fig. 6, ¶0184) between the first stack (100S) and the second stack (200),
a third stack (300) (Hiramatsu, Fig. 6, ¶0140, ¶0218) comprising:
a third semiconductor substrate (300S) and
a logic transistor (Hiramatsu, Fig. 6, ¶0504) on the third semiconductor substrate (300S), the logic transistor being configured to provide signals (e.g., through contact 301 and wiring 200T) (Hiramatsu, Fig. 6, ¶0191-¶0192, ¶0214-¶0215) to the pixel gate and the transmission gate; and
a second insulation layer (e.g., interlayer insulating film including wiring 301/302 for bonding the third substrate 300S) (Hiramatsu, Fig. 6, ¶0218) between the second stack (200) and the third stack (300).
Regarding claim 19, Hiramatsu discloses the image sensor of claim 18. Further, Hiramatsu discloses the image sensor, wherein the second stack (200) further comprises: a filling insulation layer (212) (Hiramatsu, Fig. 6, ¶0188-¶0189) in an opening penetrating through the second semiconductor substrate (200S); and a contact (120E) (Hiramatsu, Fig. 6, ¶0161, ¶0181-¶0182, ¶0188, ¶0190) that penetrates through the filling insulation layer (212) and the first insulation layer (123/124) and that is connected to the floating diffusion region (FD) (Hiramatsu, Fig. 6, ¶0161), and wherein the transmission gate (TG/TGV) (Hiramatsu, Fig. 6, ¶0152, ¶0163-¶0164) penetrates through the filling insulation layer (212) and the first insulation layer (123/124) and extends in a vertical direction.
Regarding claim 20, Hiramatsu discloses the image sensor of claim 19. Further, Hiramatsu discloses the image sensor, wherein the first stack (100) further comprises:
a pixel device isolation layer (117) (Hiramatsu, Fig. 6, ¶0160, ¶0165) in a pixel trench penetrating through the first semiconductor substrate (100S); and
a conductive layer (e.g., pad portion 120) (Hiramatsu, Fig. 6, ¶0160, ¶0170-¶0177) vertically overlapping at least a portion of the pixel device isolation layer (117) at a position adjacent to the first surface of the first semiconductor substrate (100S),
wherein the pixel device isolation layer (117) comprises a plurality of pixels (541) (Hiramatsu, Fig. 6, ¶0158-¶0162) in the first stack (100), wherein the photoelectric conversion region (PD) and the floating diffusion region (FD) are provided in at least one pixel (541) of the plurality of pixels, and
wherein the floating diffusion region (FD) surrounds the conductive layer (120) in a plan view (Hiramatsu, Fig. 7B, ¶0176).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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