DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In adhering to the 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG), Step 1 is directed to determining whether or not the claims fall within a statutory class. Herein, the claims fall within the statutory class of process, machine, or manufacture. Hence, the claims qualify as potentially eligible subject matter under 35 U.S.C. 101.
With Step 1 being directed towards a statutory category, 2019 PEG flowchart is directed to Step 2. Step 2 is a two-prong inquiry. Prong one considers whether the claims recite a judicial exception. In this case, independent claims 1, 7, and 13 recite the mental process of generating result service data, which is a process that can be performed within the human mind including the use of a computer as a tool to perform a mental process (See MPEP 2106.04(a)(2)(III)). The generation being a mental process that can be done by observation, evaluation, judgment, or opinion.
Since the claims recite an abstract idea, analysis flows to prong two. Prong two considers whether the judicial exception is integrated into a practical application. Claim 1 recites “obtaining a service data processing request from a first queue,” “obtaining to-be-processed service data corresponding to the service data processing request from the processor core via a service interface,” and “writing the result service data into a second queue for providing to the processor core.,” Claim 7 recites “writing a service data processing request…” and “reading result service data from a second queue…,” and Claim 13 recites “write a service data processing request…,” “obtain the service data processing request from the first queue,” “obtain to-be-processed service data corresponding to the service data processing request from the processor core via a service interface,” “write the result service data into a second queue…,” ”write a service data processing request into a first queue,” and “read the result service data from the second queue.” These limitations merely recite the insignificant extra-solution activity of mere data gathering through the various obtaining, writing, and reading limitations shown above (See MPEP 2106.05(g)). Further, the recited computer elements, such as the processor core, accelerator, first and second queues, and service interface of claim 1, processor core, accelerator, and first and second queue of claim 7, and the processor core, accelerator, first and second queue, and service interface of claim 13 recite merely generic computing elements (See MPEP 2106.05(f))
Claims 1, 7, and 13 do not use the listed limitations above for any application to an improvement and do not amount to significantly more than the judicial exception.
Since the claims are directed to the determined judicial exception, the analysis flows to Step 2B. Therein, the elements and combination of elements are examined in the claims to determine whether the claims as a whole amount to significantly more than the judicial exception. The additional elements, such as the processor core, accelerator, a first and second queue, and service interface merely recite generic computing apparatuses without significantly more than the judicial exception (See MPEP 2106.05(f)). Further, the acts of obtaining, reading, and writing are merely adding insignificant extra-solution activity that is well understood, routine, and conventional as indicated in MPEP 2106.05(d). Since there are no elements or ordered combination of elements that amount to significantly more than the judicial exception, the claims are not eligible subject matter under 35 U.S.C. 101.
Dependent claims 2-6, 8-12, and 14-22 do not cure the deficiencies of the independent claims as they recite elements that when considered individually or in combination with the elements of the parent claims would not amount to a practical application of the abstract idea or amount to significantly more.
For example:
Claim 2 recites “obtaining the to-be-processed service data corresponding to the service data processing request,” “reading the to-be-processed service data,” “transmitting the data obtaining information to the processor core through a service interface,” and “receiving the to-be-processed service data transmitted by the processor core.” which all amount to mere data gathering, as well as reciting the mental processes of “determining whether the to-be-processed service data corresponding to the service data processing request exists in the accelerator” and “generating data obtaining information”
Claim 3 recites “reading a register identifier in the service data processing request” which amounts to mere data gathering, insignificant extra-solution activity of “searching an accelerator register file of the accelerator for a target register corresponding to the register identifier,” and the mental processes of “determining that the to-be-processed service data corresponding to the service data processing request exists when a register status of the target register is valid” and “determining that the to-be-processed service data corresponding to the service data processing request does not exist when the register status of the target register is invalid”
Claim 4 recites “writing the register identifier in the service data processing request into an invalid register queue; reading the register identifier from the invalid register queue” which amounts to mere data gathering, as well as the mental process of generating.
Claim 5 recites “receiving the to-be-processed service data transmitted by the processor core; updating the accelerator register file based on the register identifier and the to-be-processed service data; and reading the to-be-processed service data from the accelerator register file based on the register identifier” which amounts to mere data gathering.
Claim 6 recites “receiving data ready information transmitted by the processor core; and updating the register status of the target register to valid based on the data ready information.” Which amounts to mere data gathering.
Claim 8 recites mere data gathering with “receiving, based on a service interface, data obtaining information transmitted by an accelerator, wherein the data obtaining information carries a register identifier,” “obtaining the to-be-processed service data from a core register file of the processor core based on the register identifier,” and “transmitting the to-be-processed service data to the accelerator.”
Claim 9 recites “updating the core register file based on the result service data and the register identifier,” which merely amounts to insignificant extra-solution activity.
Claim 10 recites mere data gathering with “obtaining the to-be-processed service data from the core register file of the processor core based on the register identifier,” and “transmitting the data ready information to the accelerator,” as well as the mental process of “generating data ready information based on the register identifier.”
Claim 11 recites insignificant extra-solution activity of “searching a register comparison table for register location information corresponding to the register identifier” and “searching the core register file based on the register location information for the to-be-processed service data corresponding to the register identifier.”
Claim 12 recites the mere data gathering step of “receiving the service data processing request from an upper-level service logic layer.”
Claim 14 recites the mere data gathering limitations of “read the to-be-processed service data,” “receive, based on a service interface, the data obtaining information transmitted by the accelerator, wherein the data obtaining information carries a register identifier,” “obtain the to-be-processed service data from a core register file of the processor core based on the register identifier,” and “transmit the to-be-processed service data to the accelerator; and the accelerator is further configured to receive the to-be-processed service data transmitted by the processor core,” as well as the mental processes of “determine whether the to-be-processed service data corresponding to the service data processing request exists in the accelerator” and “generate data obtaining information and transmitting the data obtaining information to the processor core through a service interface.”
Claim 15 recites “read the register identifier in the service data processing request,” which amounts to mere data gathering, the mental processes of “determine that the to-be-processed service data corresponding to the service data processing request exists when a register status of the target register is valid” and “determining that the to-be-processed service data corresponding to the service data processing request does not exist when the register status of the target register is invalid” and insignificant extra-solution activity including “search an accelerator register file of the accelerator for a target register corresponding to the register identifier.”
Claim 16 recites mere data gathering/transmission with “read the to-be-processed service data from the accelerator register file based on the register identifier” as well as insignificant extra-solution activity with “update the accelerator register file based on the register identifier and the to-be-processed service data.”
Claim 17 recites “write the register identifier in the service data processing request into an invalid register queue” and “read the register identifier from the invalid register queue”, which results to mere data gathering/transmission, as well as the mental process of “generate the data obtaining information based on the register identifier”.
Claim 18 recites “receive data ready information transmitted by the processor core,” which is mere data gathering, as well as “update the register status of the target register to valid based on the data ready information”, which is insignificant extra-solution activity.
Claim 19 recites “update the core register file based on the result service data and the register identifier” which is insignificant extra-solution activity.
Claim 20 recites “transmit the data ready information to the accelerator”, which is merely data gathering/transmission, as well as the mental process of “generate data ready information based on the register identifier”.
Claim 21 recites the insignificant extra-solution activity of “search a register comparison table for register location information corresponding to the register identifier; and search the core register file based on the register location information for the to-be-processed service data corresponding to the register identifier.”
Claim 22 recites “receive the service data processing request from an upper-level service logic layer” which amounts to mere data gathering.
As such, the dependent claims do not amount to significantly more than the judicial exception, nor do they provide a practical application for the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-10, 12, 13, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ouyang et al. (US 20200050481) in view of Dwiel et al. (US 20230092898).
Regarding claim 13, Ouyang teaches: A method / A system, comprising: a processor core configured to write a service data processing request into a first queue (the target processor core adds the generated complex computational instruction to a complex computational instruction queue par. 0054 - 0063); and an accelerator communicatively coupled to the processor core (a computational accelerator connected to each processor core par. 0045) and configured to: obtain the service data processing request from the first queue (select a complex computational instruction from the complex computational instruction queue par. 0057); obtain to-be-processed service data corresponding to the service data processing request from the processor core via a service interface (the computational accelerator executes a complex computation indicated by the complex computational identifier in the selected complex computational instruction using at least one operand as an inputted parameter par. 0060); generate result service data based on the to-be-processed service data (a computational result is obtained par. 0060 – 0061); and write the result service data into a second queue for providing to the processor core (the computational accelerator writes the obtained computational result into a complex computational result queue par. 0063); wherein the processor core is further configured to: read the result service data from the second queue (the target processor core selects a computational result in the complex computational result with the processor core identifier being the identifier of the target processing core from the complex computational result queue, and writes the computational result into a result register in the target processor core par. 0106).
Ouyang does not explicitly teach reading the result service data from the second queue, instead it teaches the selection and writing of a result from a queue into a register. The Examiner would like to note that, while being a similar process to reading results from a queue, it does not explicitly state that anything more than a selection and writing is occurring.
However, Dwiel more clearly teaches: Read the result service data from the second queue (the Z memory may be written to memory using an extraction method to move the results to the X memory and/or the Y memory, and then storing the results to system memory par. 0044, in which the instruction bugger for load/store operations and memory access interface may include a queue for load/store operations par. 0049)
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Ouyang with the teachings of Dwiel would enhance the teachings of Ouyang since the prefetcher for a coprocessor, as disclosed by Dwiel, allows for a coprocessor to issue prefetches for data associated with specific memory addresses prior to the execution of coprocessor instructions, thereby providing the processor core of Ouyang with the functionality of using a memory access interface to obtain data prior to the execution, increasing performance and efficiency.
Claims 1 and 7 are rejected using the same reasoning and rationale as claim 13 despite being more broad in scope.
Regarding claim 8, Ouyang teaches: wherein before receiving the result service data from a second queue, the method further comprises: receiving, based on a service interface, data obtaining information transmitted by an accelerator (the target processor core may decode the to-be-executed instruction when receiving the to-be-executed instruction, to obtain a computational identifier and at least one operand par. 0048), wherein the data obtaining information carries a register identifier (decoding includes obtaining a computational identifier the uniquely identifies various kinds of computation that may be executed par. 0048); obtaining the to-be-processed service data from a core register file of the processor core based on the register identifier (the target processor core selects the complex computational result from the complex computational result queue corresponding to the target processor core into at least one of: a result register in the target processor core, or a memory par. 0086 – 0087); and transmitting the to-be-processed service data to the accelerator (the computational accelerator uses the computational result obtained from executing the complex computation as the complex computational result and writes the complex computational result into the complex computational result queue, par. 0064, effectively transmitting results to the accelerator).
Regarding claim 9, Ouyang teaches: updating the core register file based on the result service data and the register identifier (the computational accelerator writing the obtained results into the result register of the target processor core par. 0083 – 0087).
Regarding claim 10, Ouyang teaches: wherein before obtaining the to-be-processed service data from the core register file of the processor core based on the register identifier, the method further comprises: generating data ready information based on the register identifier (generating a complex computational instruction using the complex computational identifier and the at least one operand, and adding the generated instruction to a complex computational instruction queue par. 0068); and transmitting the data ready information to the accelerator (the computational accelerator uses the complex computational instruction queue, par. 0068, effectively transmitting results to the accelerator).
Regarding claims 12 and 22, Dwiel teaches: wherein before writing the service data processing request into the first queue, the method further comprises: receiving the service data processing request from an upper-level service logic layer (the coprocessor may provide the coprocessor load/store operations from the instruction buffer to the memory access interface, which may include a queue for the load/store operations and control logic to select the load/store operations for execution, par. 0049, as the memory access interface acts as a logic layer).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Ouyang with the teachings of Dwiel would enhance the teachings of Ouyang since the prefetcher for a coprocessor, as disclosed by Dwiel, allows for a coprocessor to issue prefetches for data associated with specific memory addresses prior to the execution of coprocessor instructions, thereby providing the processor core of Ouyang with the functionality of using a memory access interface to obtain data prior to the execution, increasing performance and efficiency.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ouyang and Dwiel in view of Tennenhaus et al. (US 20170161066).
Regarding claim 11, Tennenhaus teaches: wherein obtaining the to-be-processed service data from the core register file of the processor core based on the register identifier comprises: searching a register comparison table for register location information corresponding to the register identifier (searching commit register map which includes information relating to segments/locations in the segments for committed instructions par. 0078 - 0081); and searching the core register file based on the register location information for the to-be-processed service data corresponding to the register identifier (a register file comprises multiple physical registers, renaming units associate each architectural register in the decoded instructions to a respective physical register in the register file, mapping operands to existing physical registers, therefore the register file can include various mapping information regarding the registers par. 0036 - 0039).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Ouyang and Dwiel with the teachings of Tennenhaus since the use of committing instructions and merging architectural-to-physical register mapping, as outlined in Tennenhaus, would enhance the prior combination by providing parallelizing of committing instructions in a processor that typically fetches instructions from memory, decodes instructions, and performs register functions.
Allowable Subject Matter
Claims 2-6, and 14-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Griffin et al. (US 8738860) which outlines accelerator circuitry containing caches that uses a multicore interface for coprocessor acceleration, Li et al. (US 20220414052) which outlines a primary and secondary processor core and a to-be-executed target program, utilizing an accelerator for implementation, and Wang et al. (US 20250199890) which outlines a memory mapped I/O interface to registers on the GPU and with commands placed into processor memory and using an agent to maintain communication between accelerators and cores but is silent regarding checking if service data request exists in an accelerator.
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/J.S.M./ Examiner, Art Unit 2198
/PIERRE VITAL/ Supervisory Patent Examiner, Art Unit 2198
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