Prosecution Insights
Last updated: September 20, 2026
Application No. 18/598,456

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Mar 07, 2024
Priority
Sep 15, 2023 — JP 2023-150438
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
364 granted / 442 resolved
+14.4% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
14 currently pending
Career history
467
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.7%
+10.7% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 442 resolved cases

Office Action

§103 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group II (claims 9-19) in the reply filed on 06/15/2026 is acknowledged. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/07/2024 has been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 9-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 9 recites “A semiconductor device comprising: a cell region including a semiconductor device…” (emphasis added). That is “a semiconductor device” is introduced twice and it is unclear whether the second introduction is referring to the previously introduced semiconductor device or a second semiconductor device separate from the first semiconductor device. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9, 10, 12-14, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kudou et al. (US Pub. 2019/0080976) in view of Hanaoka (US Pub. 2004/0102024). Regarding independent claim 9, Kudou teaches (Figs. 5A, 5B, 6; para. 0083+) a semiconductor device (100) comprising: a cell region (100A) including a semiconductor device (para. 0090); and a termination region (100E) surrounding the cell region (para. 0090), wherein the termination region includes: a metal wiring line (112) electrically connected to the semiconductor device (Fig. 6; para. 0093); a protection film (125/126) covering the metal wiring line (Fig. 6; para. 0083). Kudou is silent with respect to a stopper film. Hanaoka teaches a semiconductor device (Figs. 9, 10; para. 0072+) including a stopper film (30) having a side surface being in contact with an end portion of a protection film (40). It would have been obvious to one of ordinary skill in the art at the time of filing to include a stopper film as taught by Hanaoka within the region 100S of Kudou to arrive at the claimed invention for the purpose of improving heat sinking abilities of the semiconductor device (Hanaoka para. 0074). Re claim 10, Kudou in view of Hanaoka teaches wherein the stopper film includes an an electrically conductive film (para. 0074 – “metal”). Re claim 12, Kudou teaches wherein the protection film includes a polyimide film (para. 0053). Re claim 13, Kudou teaches wherein the semiconductor device includes a MOSFET (para. 0083). Re claim 14, Kudou in view of Hanaoka teaches another cell region; another termination region surrounding the other cell region, a first dicing line extending in a first direction between the cell region and the other cell region; and a second dicing line perpendicular to the first direction, wherein the stopper film extends in an intersection region between the first dicing line and the second dicing line (Kudou Fig. 6; Hanaoka Figs. 6, 9, 10). Re claim 16, Kudou teaches wherein a thickness of the protection film at the end portion of the protection film is less than a thickness of the protection film at a portion in contact with a side surface of the metal wiring line (Fig. 6). Re claim 18, Kudou teaches wherein a thickness of the protection film on the metal wiring line is greater than a thickness of the protection film at the end portion of the protection film (Fig. 6). Allowable Subject Matter Claims 11, 15, 17, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (assuming all 112 Rejections are successfully overcome). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 07, 2024
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.3%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 442 resolved cases by this examiner. Grant probability derived from career allowance rate.

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