Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 15, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) in view of Wallner et al. (U.S. 2019/0318955 A1, hereinafter refer to Wallner).
Regarding Claim 1: Park discloses a method of fabricating a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown below and ¶ [0003]), the method comprising:
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forming a dummy gate (111/112) and gate spacers (140) on a semiconductor region of a substrate (100) (see park, Fig.24 as shown above and ¶ [0249]);
forming an interlayer dielectric layer (182) along sides of the gate spacers (140) (see park, Fig.24 as shown above and ¶ [0253]);
forming a trench (145) having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench (see park, Fig.27 as shown above and ¶ [0276]]), forming the trench (145) including:
removing a first portion of the dummy gate (111/112), wherein a second portion of the dummy gate remains (111/112) (see park, Figs.24-25 as shown above);
forming a photoresist pattern (20/etch stop layer) on the interlayer dielectric layer (182) after (before) removing the first portion of the dummy gate (111/112), the photoresist pattern (20/etch stop layer) comprising an opening (23) that exposes upper surfaces of the second portion of the dummy gate (111/112) and the gate spacers (140) (see park, Figs.24-26 as shown above); and
removing a part of the gate spacers (140) and the second portion of the dummy gate (111/112) exposed by the opening (23) of the photoresist pattern (20/etch stop layer) (see park, Figs.24-26 as shown above); and
removing a part of the gate spacers (140) (see park, Fig.27 as shown above and ¶ [0276]), and
forming a gate structure (110/120/130) in the trench (145) (see park, Figs.28-29 as shown above),
wherein: the gate structure (110/120/130) has a lower portion and an upper portion, the upper portion of the gate structure being in the upper portion of the trench (145), the lower portion of the gate structure being in the lower portion of the trench (145), and the upper portion of the gate structure being wider than the lower portion of the gate structure (see park, Figs.28-29 as shown above),
a first one of the gate spacers (140a) has a first inner sidewall that faces a first side of the lower portion of the gate structure (110/120/130), and a second one of the gate spacers (140a) has a second inner sidewall that faces a second side of the lower portion of the gate structure (110/120/130), the first inner sidewall being spaced apart from the second inner sidewall by a first distance (W1/L1) (see park, Figs.2-3A and 28-29 as shown above), and
wherein the upper portion of the gate structure (W3/L3) has a width that is greater than the first distance (W1/L1) (see park, Figs.2-3A and 28-29 as shown above).
Park is silent upon explicitly disclosing wherein forming a photoresist pattern on the interlayer dielectric layer after removing the first portion of the dummy gate, the photoresist pattern comprising an opening that exposes upper surfaces of the second portion of the dummy gate and the gate spacers; and
removing a part of the gate spacers and the second portion of the dummy gate exposed by the opening of the photoresist pattern.
For support see Wallner, which teaches wherein forming a photoresist pattern (601) on the interlayer dielectric layer (301) after removing the first portion of the dummy gate (215), the photoresist pattern (601) comprising an opening (603) that exposes upper surfaces of the second portion of the dummy gate (211/213) and the gate spacers (217) (see Wallner, Figs.4-6 as shown below); and
removing a part of the gate spacers (217) and the second portion of the dummy gate (211/213) exposed by the opening (603) of the photoresist pattern (601) (see Wallner, Figs.6-7 as shown below).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Wallner to enable the dummy gate structure Park to be removed according to the teachings of Wallner because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of removing the dummy gate structures of Park and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Furthermore, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention was made to enable the known photoresist pattern for removing the dummy gate structure, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Note: selection of any order of performing process steps for removing the dummy gate structure and a portion of the gate spacer of Park is prima facie obvious in the absence of new or unexpected results.
Regarding Claim 11: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 1 as above. The combination of Park and Wallner further teaches wherein: forming the trench (145) includes making upper portions of gate spacers (140) narrower (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and
sides of the upper portion of the trench (145) are defined by sidewalls of upper portions of the gate spacers (140) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Regarding Claim 12: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 11 as above. The combination of Park and Wallner further teaches wherein: forming the trench (145) includes performing at least one etch operation to remove the part of the gate spacers (140) and the dummy gate (111/112) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and
the gate spacers (140) are etched so that the sidewalls of the upper portion of the trench (145) are aligned with a point between inner sides and outer sides of the gate spacers (140) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Regarding Claim 13: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 1 as above. The combination of Park and Wallner further teaches wherein: the gate structure (110/120/130) includes a filling conductor (130) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the filling conductor (130) is formed to have a lower portion and an upper portion (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the upper portion of the filling conductor (130) is in the upper portion of the trench (145) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the lower portion of the filling conductor (130) is in the lower portion of the trench (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above), and
the upper portion of the filling conductor (130) is wider than the lower portion of the filling conductor (130) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Regarding Claim 14: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 1 as above. The combination of Park and Wallner further teaches wherein forming the gate structure (110/120/130) includes:
forming a gate dielectric layer (110), the gate dielectric layer (110) being formed to have a substantially uniform first thickness (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above);
forming a work function layer (120) on the gate dielectric layer (110), the work function layer (120) being formed to have a substantially uniform second thickness (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); and
forming a filling conductor (130) on the work function layer (120), the filling conductor (130) being formed to fill a remaining part of the trench (145) not occupied by the gate dielectric layer (110) and the work function layer (120), and having a greater electrical conductivity than the work function layer (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Claim(s) 2-10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) and Wallner et al. (U.S. 2019/0318955 A1, hereinafter refer to Wallner) as applied to claim 1 above, and further in view of Kuo et al. (U.S. 2021/0234021 A1, hereinafter refer to Kuo).
Regarding Claim 2: Park as modified teaches a method of fabricating a semiconductor device as applied to claim 1 above. The combination of Park and Wallner is silent upon explicitly disclosing wherein: forming the trench includes removing a part of the interlayer dielectric layer,
sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and
a minimum separation of the sidewalls is greater than a distance between outer sides of the gate spacers.
For support see Kuo, which teaches wherein: forming the trench includes removing a part of the interlayer dielectric layer (810A) (see Kuo, Fig.8 as shown below and ¶ [0018]),
sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer (810A) (see Kuo, Fig.8 as shown below and ¶ [0018]), and
a minimum separation of the sidewalls is greater than a distance between outer sides of the gate spacers (810B) (see Kuo, Fig.8 as shown below and ¶ [0018]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Wallner and Kuo to enable forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls to be greater than a distance between outer sides of the gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed.
Regarding Claim 3: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park, Wallner, and Kuo further teaches wherein: forming the trench includes performing at least one etch operation to remove the part of the interlayer dielectric layer (810A), the part of the gate spacers (810B), and the dummy gate (307) (see Kuo, Fig.8 as shown above and ¶ [0018]), and
the part of the interlayer dielectric layer (810A) is etched so that the upper portion of the trench is wider than the distance between outer sides of the gate spacers (810B) (see Kuo, Fig.8 as shown above and ¶ [0018]).
Regarding Claim 4: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park, Wallner, and Kuo further teaches wherein forming the trench includes forming the sidewalls to have an angle D1 relative to a major plane of a surface of the substrate (101) that ranges from 90 degrees to 120 degrees (see Kuo, Fig.8 as shown above).
Regarding Claim 5: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 4 as above. The combination of Park, Wallner, and Kuo further teaches wherein the upper portion of the gate structure (605/607) is formed to have sides that have the angle D1 relative to the major plane of the surface of the substrate (101) (see Kuo, Fig.8 as shown above).
Regarding Claim 6: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 5 as above. The combination of Park, Wallner, and Kuo further teaches wherein D1 is greater than 90 degrees (see Kuo, Fig.8 as shown above).
Regarding Claim 7: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 2 as above. The combination of Park, Wallner, and Kuo further teaches wherein forming an insulating layer (150) on top of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
wherein the gate spacers (140a and 140b) have a height that is at least ⅓ of an overall distance from a bottom of the gate spacers (140a and 140b) to a top of the insulating layer (150) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above).
Regarding Claim 8: Park as modified teaches a method of fabricating a semiconductor device as applied to claim 1 above. The combination of Park and Wallner is silent upon explicitly disclosing wherein: forming the trench includes removing a part of the interlayer dielectric layer,
sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and
a minimum separation of the sidewalls is approximately the same as a distance between outer sides of the gate spacers.
For support see Kuo, which teaches wherein: forming the trench includes removing a part of the interlayer dielectric layer (710A) (see Kuo, Fig.7 as shown above and ¶ [0018]),
sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer (710A) (see Kuo, Fig.7 as shown above and ¶ [0018]), and
a minimum separation of the sidewalls is approximately the same as a distance between outer sides of the gate spacers (710B) (see Kuo, Fig.7 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Wallner, and Kuo to enable forming the trench includes removing a part of the interlayer dielectric layer, sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and a minimum separation of the sidewalls to be approximately the same as a distance between outer sides of the gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed.
Regarding Claim 9: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 8 as above. The combination of Park, Wallner, and Kuo further teaches wherein: forming the trench includes performing at least one etch operation to remove the part of the interlayer dielectric layer (710A/810A), the part of the gate spacers (710B/810B), and the dummy gate (307) (see Kuo, Fig.8 as shown above and ¶ [0018]), and
the part of the interlayer dielectric layer (710A/810A) is etched so that the sidewalls of the interlayer dielectric layer (710A/810A) in the upper portion of the trench are substantially aligned with outer sides of the gate spacers (810B) (see Kuo, Fig.8 as shown above and ¶ [0018]).
Regarding Claim 10: Park as modified teaches a method of fabricating a semiconductor device as set forth in claim 8 as above. The combination of Park, Wallner, and Kuo further teaches wherein forming an insulating layer (150) on top of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
wherein the gate spacers (140a and 140b) have a height that is at least ⅓ of an overall distance from a bottom of the gate spacers (140) to a top of the insulating layer (150) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above).
Claim(s) 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) in view of LEE et al. (U.S. 2016/0163820 A1, hereinafter refer to LEE).
Regarding Claim 15: Park discloses a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above and ¶ [0003]) comprising:
a semiconductor region having a channel region therein (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above);
a gate structure (110/120/130) adjacent to the channel region (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above);
a first gate spacer (140) at a first side of the gate structure (110/120/130) and a second gate spacer (140) at a second side of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above); and
an interlayer dielectric layer (182) along sides of the first and second gate spacers (140) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
wherein: the gate structure (110/120/130) has a lower portion and an upper portion, a width of the upper portion of the gate structure (110/120/130) being different from a width of the lower portion of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the first gate spacer (140a) has a first inner sidewall that faces a first side of the lower portion of the gate structure (110/120/130), and the second gate spacer (140a) has a second inner sidewall that faces a second side of the lower portion of the gate structure (110/120/130), the first inner sidewall being spaced apart from the second inner sidewall by a first distance (W1/L1) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the upper portion of the gate structure (110/120/130) has a width (W3/L3) that is greater than the first distance (W1/L1) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
the gate structure (110/120/130) comprises a gate dielectric layer (110) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Park is silent upon explicitly disclosing wherein at least one of the first gate spacer or the second gate spacer comprises an uppermost surface covered by the gate dielectric layer.
For support see LEE, which teaches wherein at least one of the first gate spacer (232) or the second gate spacer (234) comprises an uppermost surface covered by the gate dielectric layer (292) (see LEE, Figs.2N and 3 as shown below and ¶ [0046]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and LEE to enable at least one of the first gate spacer or the second gate spacer to comprises an uppermost surface covered by the gate dielectric layer as taught by LEE in order to improve AC performance.
Regarding Claim 19: Park as modified teaches a semiconductor device as set forth in claim 15 as above. The combination of Park and LEE further teaches wherein an insulating layer (150) on top of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above),
wherein the first and second gate spacers (140a/140b) have a height that is at least ⅓ of an overall distance from a bottom of the first and second gate spacers (140a/140b) to a top of the insulating layer (150) (see Park, Figs.2, 3A, 12-13, and 26-31 as shown above).
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) and LEE et al. (U.S. 2016/0163820 A1, hereinafter refer to LEE) as applied to claim 15 above, and further in view of Kuo et al. (U.S. 2021/0234021 A1, hereinafter refer to Kuo).
Regarding Claim 16: Park as modified teaches a semiconductor device as applied to claim 15 above. The combination of Park and LEE is silent upon explicitly disclosing wherein the upper portion of the gate structure has a width that is greater than a distance between outer sidewalls of the first and second gate spacers.
For support see Kuo, which teaches wherein the upper portion of the gate structure (605/607) has a width that is greater than a distance between outer sidewalls of the first and second gate spacers (810B) (see Kuo, Fig.8 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, LEE, and Kuo to enable the upper portion of the gate structure to have a width that is greater than a distance between outer sidewalls of the first and second gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed.
Regarding Claim 17: Park as modified teaches a semiconductor device as applied to claim 15 above. The combination of Park and LEE is silent upon explicitly disclosing wherein the upper portion of the gate structure has a width that is approximately the same as a distance between outer sides of the first and second gate spacers.
For support see Kuo, which teaches wherein the upper portion of the gate structure (605/607) has a width that is approximately the same as a distance between outer sides of the first and second gate spacers (710B) (see Kuo, Fig.7 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, LEE, and Kuo to enable the upper portion of the gate structure to have a width that is approximately the same as a distance between outer sides of the first and second gate spacers as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed.
Claim(s) 20 -21 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2015/0187946 A1, hereinafter refer to Park) in view of Kuo et al. (U.S. 2021/0234021 A1, hereinafter refer to Kuo).
Regarding Claim 20: Park discloses a semiconductor device (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above and ¶ [0003]) comprising:
a semiconductor region (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above);
a gate structure (110/120/130) on the semiconductor region (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above);
an insulating layer of a dielectric material (150) contacting a top of the gate structure (110/120/130) and extending across a full width of the top of the gate structure (110/120/130) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above);
a first gate spacer (140) and a second gate spacer (140) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above); and
an interlayer dielectric layer (182) along sides of the first and second gate spacers (140) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
wherein: the gate structure (110/120/130) has a lower portion and an upper portion (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
the upper portion extending vertically from the lower portion to the insulating layer (150), and having a second width (W3/L3) that is greater than the first width (W1/L1) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
the first gate spacer (140) has a first inner sidewall that faces a first side of the lower portion of the gate structure (110/120/130), and the second gate spacer (140) has a second inner sidewall that faces a second side of the lower portion of the gate structure (110/120/130), the first inner sidewall being spaced apart from the second inner sidewall by a first distance (W1/L1) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above), and
the insulating layer (150) has a width (W3/L3) that is greater than the first distance (W1/L1) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above),
the gate structure (110/120/130) comprises a gate dielectric layer (110) (see Park, Figs.2, 3A, 12-13, and 24-31 as shown above).
Park is silent upon explicitly disclosing wherein at least one of the first gate spacer or the second gate spacer comprises an uppermost surface covered by the gate dielectric layer.
For support see LEE, which teaches wherein at least one of the first gate spacer (232) or the second gate spacer (234) comprises an uppermost surface covered by the gate dielectric layer (292) (see LEE, Figs.2N and 3 as shown above and ¶ [0046]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and LEE to enable at least one of the first gate spacer or the second gate spacer to comprises an uppermost surface covered by the gate dielectric layer as taught by LEE in order to improve AC performance.
The combination of Park and LEE is silent upon explicitly disclosing wherein the lower portion extending vertically between the first and second gate spacers and having a first width.
For support see Kuo, which teaches wherein the lower portion extending vertically between the first and second gate spacers (710B/810B) and having a first width (see Kuo, Fig.7 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, LEE, and Kuo to enable the lower portion to be extend vertically between the first and second gate spacers and having a first width as taught by Kuo in order to increase gate contact area which in turn can improve metal filling uniformity and increase alignment tolerance and to reduce gate capacitance between gate electrode and the underlying channel region which in turn increases device speed.
Regarding Claim 21: Park as modified teaches a semiconductor device as set forth in claim 20 as above. The combination of Park, LEE, and Kuo further teaches wherein each of the first gate spacer (132) and the second gate spacer (134) further comprises an outermost surface flush with an outermost surface of the gate dielectric layer (192) (see LEE, Fig.2N as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
