Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4 and 6-8 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (U.S. Patent Pub. No. 2024/0274679).
Regarding Claim 1
FIG. 2 of Shin discloses a semiconductor structure comprising: a fork sheet transistor located on a frontside of a semiconductor [0022] device layer (F1) and comprising a plurality of semiconductor channel material nanosheets (NSS), a gate structure (160) contacting each semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets, and source/drain regions (130); a backside power rail located on a backside of the semiconductor device layer; a via-to-backside power rail (VBPR) structure (DBC) in electrical contact with the backside power rail (BPW) and one of the source/drain regions of the fork sheet transistor; and a dielectric layer (BDI) separating the VBPR structure from each of the gate structure, the plurality of semiconductor channel material nanosheets, the semiconductor device layer and the source/drain region that is in electrical contact with the backside power rail.
Regarding Claim 4
FIG. 2 of Shin discloses the VBPR structure (DBC) includes a merged frontside source/drain contact structure in direct physically contact with a topmost surface of the source/drain region (130) that is in electrical contact with the backside power rail.
Regarding Claim 6
FIG. 2A of Shin discloses the dielectric layer lands on a surface of the backside power rail.
Regarding Claim 7
FIG. 2B of Shin discloses a frontside back-end-of-the-line (BEOL) structure (CB) located above the transistor, wherein the frontside BEOL structure is in electrical contact with the gate structure of the transistor by a frontside gate contact structure.
Regarding Claim 8
FIG. 2 of Shin discloses the VBPR structure is in contact with the frontside BEOL structure.
Claims 1, 5, 10, 13, 14 and 19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam (U.S. Patent Pub. No. 2025/0120165).
Regarding Claim 1
FIG. 4 of Nam discloses a semiconductor structure comprising: a fork sheet transistor located on a frontside of a semiconductor device layer (FA) and comprising a plurality of semiconductor channel material nanosheets (NS), a gate structure (125) contacting each semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets, and source/drain regions (SD, FIG. 3); a backside power rail located on a backside of the semiconductor device layer; a via-to-backside power rail (VBPR) structure (130) in electrical contact with the backside power rail (230) and one of the source/drain regions of the fork sheet transistor; and a dielectric layer (132) separating the VBPR structure from each of the gate structure, the plurality of semiconductor channel material nanosheets, the semiconductor device layer and the source/drain region that is in electrical contact with the backside power rail.
Regarding Claim 5
FIG. 4 of Nam discloses the VBPR structure (130) extends into the backside power rail (230).
Regarding Claim 10
FIG. 4 of Nam discloses semiconductor structure comprising: a fork sheet transistor located on a frontside of a semiconductor device layer (FA) and comprising a plurality of semiconductor channel material nanosheets (NS), a gate structure (125) contacting each semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets, and source/drain regions (SD); a backside power rail located on a backside of the semiconductor device layer; a via-to-backside power rail (VBPR) structure (130) located in a non-active device area and in electrical contact with the backside power rail (230) and a topmost surface and a sidewall surface of one of the source/drain regions of the fork sheet transistor (FIG. 24); and a dielectric layer (132) separating the VBPR structure from each of the gate structure and the plurality of semiconductor channel material nanosheets.
Regarding Claim 13
FIG. 24 of Nam discloses the VBPR structure (130+CM+CA1) includes a merged frontside source/drain contact structure in direct physically contact with a topmost surface of the source/drain region that is in electrical contact with the backside power rail.
Regarding Claim 14
FIG. 4 of Nam discloses the VBPR structure (130) extends into the backside power rail (230).
Regarding Claim 19
FIG. 4 of Nam discloses the dielectric layer (132) separates the VBPR structure (130) from the semiconductor device layer (FA).
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 3, 11 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Nam, in view of Jo (U.S. Patent Pub. No. 2024/0274677).
Regarding Claim 2
Nam discloses Claim 1.
Nam is silent with respect to “an upper portion of the VBPR structure is present in a middle-of-the-line (MOL) dielectric layer, and the upper portion of the VBPR structure directly contacts the MOL dielectric layer”.
FIG. 3 of Jo discloses a similar semiconductor structure, wherein an upper portion of the VBPR structure (WVPR) is present in a middle-of-the-line (MOL) dielectric layer (168), and the upper portion of the VBPR structure directly contacts the MOL dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Nam, as taught by Jo. The ordinary artisan would have been motivated to modify Nam in the above manner for purpose of improving the reliability of the integrated circuit device ([0004] of Jo).
Regarding Claim 3
FIG. 3 of Jo discloses the upper portion of the VBPR structure that is present in the MOL dielectric layer has a shape that differs from a shape of a remaining portion of the VBPR structure.
Regarding Claim 11
Nam discloses Claim 10.
Nam is silent with respect to “an upper portion of the VBPR structure is present in a middle-of-the-line (MOL) dielectric layer, and the upper portion of the VBPR structure directly contacts the MOL dielectric layer”.
FIG. 3 of Jo discloses a similar semiconductor structure, wherein an upper portion of the VBPR structure (WVPR) is present in a middle-of-the-line (MOL) dielectric layer (168), and the upper portion of the VBPR structure directly contacts the MOL dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Nam, as taught by Jo. The ordinary artisan would have been motivated to modify Nam in the above manner for purpose of improving the reliability of the integrated circuit device ([0004] of Jo).
Regarding Claim 12
FIG. 3 of Jo discloses the upper portion of the VBPR structure that is present in the MOL dielectric layer has a shape that differs from a shape of a remaining portion of the VBPR structure.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Nam, in view of Yun (TW 202425273, machine-translation provided).
Regarding Claim 9
Nam discloses Claim 1.
Nam is silent with respect to “the dielectric layer has a topmost surface that is substantially coplanar with a topmost surface of the gate structure, and a bottommost surface that lands on the backside power rail”.
FIG. 14 of Yun discloses a similar semiconductor structure, wherein the dielectric layer (25) has a topmost surface that is substantially coplanar with a topmost surface of the gate structure, and a bottommost surface that lands on the backside power rail.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Nam, as taught by Yun. The ordinary artisan would have been motivated to modify Nam in the above manner for purpose of reducing capacitance and leaking between gate structures and source/drain features.
Regarding Claim 18
Nam discloses Claim 10.
Nam is silent with respect to “the dielectric layer has a topmost surface that is substantially coplanar with a topmost surface of the gate structure, and a bottommost surface that lands on the backside power rail”.
FIG. 14 of Yun discloses a similar semiconductor structure, wherein the dielectric layer (25) has a topmost surface that is substantially coplanar with a topmost surface of the gate structure, and a bottommost surface that lands on the backside power rail.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Nam, as taught by Yun. The ordinary artisan would have been motivated to modify Nam in the above manner for purpose of reducing capacitance and leaking between gate structures and source/drain features.
Claims 10 and 15-17 rejected under 35 U.S.C. 103 as being unpatentable over Shin, in view of Hong (U.S. Patent Pub. No. 2024/0079330).
Regarding Claim 10
FIG. 2 of Shin discloses a semiconductor structure comprising: a fork sheet transistor located on a frontside of a semiconductor device layer (F1) and comprising a plurality of semiconductor channel material nanosheets (NSS), a gate structure (160) contacting each semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets, and source/drain regions (130); a backside power rail (BPW) located on a backside of the semiconductor device layer; a via-to-backside power rail (VBPR) structure (DBC) located in a non-active device area and in electrical contact with the backside power rail and a sidewall surface of one of the source/drain regions of the fork sheet transistor; and a dielectric layer (BDI) separating the VBPR structure from each of the gate structure and the plurality of semiconductor channel material nanosheets.
Shin is silent with respect to the via-to-backside power rail (VBPR) structure in electrical contact with a topmost surface of one of the source/drain regions of the fork sheet transistor.
FIG. 6 of Hong discloses a similar semiconductor structure, wherein the via-to-backside power rail (VBPR) structure (648) in electrical contact with a topmost surface and a sidewall surface of one of the source/drain regions (126) of the fork sheet transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shin, as taught by Hong. The ordinary artisan would have been motivated to modify Shin in the above manner for purpose of an integrated circuit device including conductors having a low contact resistance ([0002] of Hong).
Regarding Claim 15
FIG. 2A of Shin discloses the dielectric layer lands on a surface of the backside power rail.
Regarding Claim 16
FIG. 2B of Shin discloses a frontside back-end-of-the-line (BEOL) structure (CB) located above the transistor, wherein the frontside BEOL structure is in electrical contact with the gate structure of the transistor by a frontside gate contact structure.
Regarding Claim 17
FIG. 2 of Shin discloses the VBPR structure is in contact with the frontside BEOL structure.
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Nam, in view of Son (U.S. Patent Pub. No. 2023/0163073).
Regarding Claim 20
Nam discloses Claim 10.
Nam is silent with respect to “the VBPR structure directly contacts a sidewall of the semiconductor device layer”.
FIG. 2 of Son discloses a similar semiconductor structure, wherein the VBPR structure (52) directly contacts a sidewall of the semiconductor device layer (10).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Nam, as taught by Son. The ordinary artisan would have been motivated to modify Nam in the above manner for purpose of improving the reliability of the integrated circuit device ([0004] of Son).
Pertinent Art
US 20240063122, 20250157896, and CN 202410468516.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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