DETAILED ACTION
This application, 18/599239, attorney docket ICYP0012USA, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Invention and Collaboration Laboratory, Inc., and claims priority from provisional application 63451236, filed 03/10/2023 Claims 1-23 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claims 1 and 9 recite, “an active region defined based on the bulk semiconductor substrate.” It is not clear how the active region is being limited.
Claim 1 recites the limitation “along the length of the active region." There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites, “with an original semiconductor surface” it is not clear how the limitation restricts the device.
Claims 2-19 depend from claims 1 or 9 and include the same depends as the parent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, 7, 10, 18, 19 and 21 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Hamaguchi (U.S. 2006/0131657).
As for claim 1.
Hamaguchi teaches in figure 1, a MOS (Metal-Oxide-Semiconductor) transistor comprising:
a bulk semiconductor substrate with a semiconductor surface (40, p-doped to 42);
an active region (between STIs 11) defined based on the bulk semiconductor substrate;
a gate structure (13a) within the active region and above the semiconductor surface;
a transistor body (21/27/28) within the active region and under the semiconductor surface;
a source region (21/27 left) electrically coupled to a channel region (28) within the transistor body;
a drain region (21/27 right) electrically coupled to the channel region within the transistor body;
and a localized isolating layer (17) extending along the length of the active region and under the transistor body (extends both across the figure and into the page);
wherein the localized isolating layer at least partially isolates the transistor body from the bulk semiconductor substrate, and a bottom of the source region and a bottom of the drain region abut against the localized isolating layer. (17 is an insulator between the s/d and the well, so isolates that portion from direct current flow into the well) .
As for claim 4,
Hamaguchi teaches the MOS transistor in claim 1, and teaches that the localized isolating layer has a semiconductor opening from which the transistor body is electrically coupled to the bulk semiconductor substrate. (figure 1).
As for claim 6,
Hamaguchi teaches the MOS transistor in claim 1, and teaches a shallow trench isolation region (11) surrounding the active region and the localized isolating layer.
As for claim 7.
The MOS transistor in claim 1, further comprising a spacer structure (vertical portions of 17 that abut the STI) at least partially surrounding the active region, wherein the spacer structure is encompassed by the shallow trench isolation region.
As for claim 9,
Hamaguchi teaches ion figure 1, a CMOS (complementary Metal-Oxide-Semiconductor) circuit, comprising:
a bulk semiconductor substrate (40) with an original semiconductor surface;
a first active region (between STIs 11 at 43) and a second active region (between STIs 11 at 44) formed based on the bulk semiconductor substrate;
a PMOS (p-type Metal-Oxide-Semiconductor) transistor formed in the first active region (at 28 left side);
a first localized isolating layer (17) under the PMOS transistor and at least partially isolating the PMOS transistor from the bulk semiconductor substrate (17 is an insulator between the s/d and the well, so isolates that portion from direct current flow into the p-well);
an NMOS (n-type Metal-Oxide-Semiconductor) transistor formed in the second active region (at 28 right side); and
a second localized isolating layer (17) under the NMOS transistor and at least partially isolating the NMOS transistor from the bulk semiconductor substrate. (17 is an insulator between the s/d and the well, so isolates that portion from direct current flow into the N-well);
As for claim 10,
Hamaguchi teaches the CMOS circuit in claim 9, further comprising:
a first shallow trench isolation region (11) surrounding the first active region and the first localized isolating layer;
and a second shallow trench isolation region (11) surrounding the second active region and the second localized isolating layer.
As for claim 18,
Hamaguchi makes obvious the CMOS circuit in claim 17, and teaches in figure 1, that a bottom of the transistor body abuts against the first localized isolating layer.
As for claim 19,
Hamaguchi teaches in figure 1, a CMOS circuit, comprising:
a bulk semiconductor substrate (40) with a first active region (between STIs 11 at 43) and a second active region (between STIs 11 at 44);
a set of PMOS transistors (at 28) formed in the first active region; and
a set of NMOS transistors (at 28) formed in the second active region;
wherein a first localized isolation layer extends along the length of the first active region and at least partially isolates the PMOS transistors from the bulk semiconductor substrate (17 is an insulator between the s/d and the well, so isolates that portion from direct current flow into the p-well);
wherein a second localized isolation layer extends along the length of the second active region and at least partially isolates the NMOS transistors from the bulk semiconductor substrate. (17 is an insulator between the s/d and the well, so isolates that portion from direct current flow into the p-well).
As for claim 21,
Hamaguchi teaches the MOS circuit in claim 19, and teaches in figure 1, a first STI (shallow trench isolation) region (11) surrounds the first active region, and a second STI region (11) surrounds the second active region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 5, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hamaguchi.
As for claim 2,
Hamaguchi teaches the MOS transistor in claim 1, but does not teach a vertical length of the transistor body is 5~10nm, and a length of the active region is greater than a width of the active region.
However vertical length of the body is a result dependent variable that defines the junction depth (Hamaguchi, [0038]) and the length of the active region determines at least the current capacity.
Because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the claimed dimensions and arrive at the claim limitation because one skilled would select the lengths for the design requirements of the device.
As for claim 5,
Hamaguchi teaches the MOS transistor in claim 4, and makes obvious that a width of the semiconductor opening along the length of the active region is 1~3nm.
The opening defines the channel length which is a result dependent variable that defines the threshold voltage.
Because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the claimed dimensions and arrive at the claim limitation because one skilled would select the length for the design requirements of the device.
As for claim 16,
Hamaguchi teaches the CMOS circuit in claim 9, and makes obvious a length of the first active region is greater than a width of the first active region, and the first localized isolating layer extends along the length of the first active region; and
a length of the second active region is greater than a width of the second active region, and the second localized isolating layer extends along the length of the second active region.
The relative dimensions are result-dependent variable that control the electrical characteristics of the device including leakage, balances voltages and currents.
Because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the claimed dimensions and arrive at the claim limitation b
As for claim 17,
The CMOS circuit in claim 9, wherein the PMOS transistor comprises a transistor body under the original semiconductor surface, and a vertical length of the transistor body is 5~10nm.
However vertical length of the body is a result dependent variable that defines the junction depth (Hamaguchi, [0038]) and the length of the active region determines at least the current capacity.
Because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the claimed dimensions and arrive at the claim limitation because one skilled would select the lengths for the design requirements of the device.
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hamaguchi in view of Fazan (U.S. 2008/0237714).
As for claim 22,
Hamaguchi teaches the CMOS circuit in claim 21, but does not teach that the CMOS circuit is a SRAM (static random-access memory) cell, and the distance between one PMOS transistor and one NMOS transistor adjacent to the one PMOS transistor is not greater than 3F, wherein F is the minimum feature size.
However, Fazan teaches in figures 1B, 4 and 7, an SRAM [0003]) cell and the distance between one PMOS transistor and one NMOS transistor adjacent to the one PMOS transistor is not greater than 3F, wherein F is the minimum feature size. (distance between word lines is 3F Fazan [0037]).
It would have been obvious to one skilled in the art at the effective filing date of this application use the spacing of Fazan in the device of Hamaguchi because it provides a standard size for a cell that minimizes the cell size without creating leakage or interference. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 23,
Hamaguchi teaches the CMOS circuit in claim 19, but does not teach a length of the first active region is greater than a width of the first active region, and a length of the second active region is greater than a width of the second active region.
However, Fazan teaches in figures 1B, 4 and 7 a length of the first active region is greater than a width of the first active region, and a length of the second active region is greater than a width of the second active region. (1f and 3f [0037, 0049]).
It would have been obvious to one skilled in the art at the effective filing date of this application use the spacing of Fazan in the device of Hamaguchi because it provides a standard size for a cell that minimizes the cell size without creating leakage or interference. One skilled in the art would have combined these elements with a reasonable expectation of success.
Allowable Subject Matter
Claims 3, 8, 11, 12, 13, 14, 15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 3, the prior art does not teach or make obvious an isolation region that abuts the source/drain and fully isolates the transistor body from the substrate.
Examiner notes that his interpretation of claim 1 excludes device build on an SOI substrate because claim 1 appears to require that the active area is a part of the bulk substrate, and an epitaxial or bonded active region used above a SOI buried oxide is not part of the bulk substrate. Examiner’s interpretation is based on the applicant’s disclosure, which cuts a channel in the substrate and fills it with dielectric.
As for claim 8, Hamaguchi teaches the MOS transistor in claim 7, a nitride spacer surrounding the oxide spacer. (17 is nitride [0039]). But the prior art does not teach the spacer structure comprises an oxide spacer and a nitride spacer surrounding the active region .
As for claim 11, Hamaguchi teaches the CMOS circuit in claim 9, but does not teach that the first localized isolating layer fully isolates the PMOS transistor from the bulk semiconductor substrate AND the second localized isolating layer only partially isolates the NMOS transistor from the bulk semiconductor substrate.
Claim 12 depends from allowable claim 11 and includes the same novel feature.
As for claim 13, Hamaguchi teaches the CMOS circuit in claim 9, and teaches the first localized isolating layer only partially isolates the PMOS transistor from the bulk semiconductor substrate, but the prior art does not teach that second localized isolating layer fully isolates the NMOS transistor from the bulk semiconductor substrate.
Claim 14 depends from allowable claim 12 and includes the same novel feature.
As for claim 15. the prior art does not teach the first localized isolating layer fully isolates the PMOS transistor from the bulk semiconductor substrate, and the second localized isolating layer fully isolates the NMOS transistor from the bulk semiconductor substrate.
As for claim 20, the prior art does not teach the first localized isolating layer fully isolates the set of PMOS transistors from the bulk semiconductor substrate, and the second localized isolating layer only partially isolates the set of NMOS transistors from the bulk semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893
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