DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/1/2025, 8/6/2025, 7/7/2026 are being considered by the examiner.
Status of Claims
This office action is in response to "Claims filed on 6/5/2026". Applicants’ amendments of claims 1, 2, 4, 6, 15-18 with the same reply have been entered by the Examiner. Upon entry of the amendments, claims 1-19 are pending wherein claims 1 and 16 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “on” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently discloses a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “a function word indicating close proximity” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-7, 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US 2022/0037510 A1 hereinafter Cheng).
Regarding Claim 1, Cheng discloses in Fig 1B: A semiconductor device,
comprising:
a substrate (104) having an active region (110a/b);
a recess gate structure (112a) disposed in the substrate and intersecting the
active region (See Fig 1B);
a conductive pillar (126) disposed over the substrate and electrically connected
to the active region (See Fig 1B);
a landing pad (130) disposed on the conductive pillar and electrically connected
to the conductive pillar (126); and
a stack of dielectric layers (118/117) disposed over the substrate (104) and
laterally surrounding the conductive pillar and the landing pad (See Fig 1B) [0021-0022,
0024-0026, 0032-0036],
a contact structure (122/124) disposed between the substrate (101) and the conductive pillar (126), wherein the contact structure is electrically connected to the active region (K) and the conductive pillar (126);
wherein the contact structure (122/124) is in contact between the active region (110A/110B) of the substrate and the conductive pillar (126); wherein the contact structure comprises a conductive column (124 – first layer) and a barrier layer (124 – second layer; Examiner notes that 124 could comprise multiple layers in [0028]) covering a sidewall and a bottom surface of the conductive column (124 – first layer); wherein a top surface of the conductive column (124- first layer) and a barrier layer (124-second layer) are coplanar with each other and are in contact with the conductive pillar (126) [0123-0133].
Regarding Claim 2, Cheng discloses in Fig 1B: The semiconductor device of
claim 1, wherein the recess gate structure comprises:
a gate insulating layer (114/138) conformally formed in a trench disposed in the substrate (104) at a position that the gate insulating layer (114/138) is formed on side surfaces and a bottom surface of the trench (See Fig 1B);
a work function layer (140) formed on the gate insulating layer (114/138) and in
the trench (see Fig 1B);
a first conductive layer (144) formed on the work function layer and in the trench;
and a capping layer (148) formed on the first conductive layer and in the trench.
Regarding Claim 3, Cheng discloses in Fig 1B: The semiconductor device of
claim 2, further comprising: a liner layer (150/152 – first layer) conformally disposed on the first conductive layer (144) and on the gate insulating layer (114/138), and disposed
between the capping layer (148) and the first conductive layer (144); and
a second conductive layer (152 – second layer) disposed between the capping layer (148) and the liner layer (150/152-first layer) [0040]. In [0040], Cheng discloses that 152 comprises multiple layers.
Regarding Claim 4, Cheng discloses in Fig 1B: The semiconductor device of
claim 3, wherein the liner layer (150/152- first layer) is formed in a U-shaped cross-sectional profile [0040-0041].
Regarding Claim 5, Cheng discloses in Fig 1B: The semiconductor device of
claim 4, wherein a top surface of the liner layer (150/152-first layer) is substantially coplanar with a bottom surface of the capping layer (148) [0040].
Regarding Claim 6, Cheng discloses in Fig 1B: The semiconductor device of
claim 5, wherein a top surface of the second conductive layer (152 – second layer), the top surface of the liner layer (150/152-first layer) and the bottom surface of the capping layer are substantially coplanar (148) [0040].
Regarding Claim 7, Cheng discloses in Fig 1B: The semiconductor device of
claim 6, wherein the liner layer (150/152 – first layer can include a nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), other suitable nitride materials) is formed of a material having an etching selectivity (different materials have different etching sensitivities) to the gate insulating layer (114/138) silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon
oxycarbon nitride (SiOCN), and silicon germanium oxide/HK layer) [0022, 0033].
Regarding Claim 9, Cheng discloses in Fig 1B: The semiconductor device of claim 3, wherein the second conductive layer is formed of molybdenum [0044].
Regarding Claim 10, Cheng and Chien disclose: The semiconductor device of
claim 9, The limitation " wherein the second conductive layer is formed by a chemical vapor deposition process." in claim 10 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product "gleaned" from the process steps, which must be determined in a "product by process" claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in "product by process" claim or not.
Regarding Claim 11, Cheng disclose: The semiconductor device of claim 3, wherein a top surface of the gate insulating layer (114/138) is located at a vertical level higher than a bottom surface of the active region (110A/110B) See Fig 1B.
Regarding Claim 12, Cheng discloses in Fig 1B: The semiconductor device of
claim 11, wherein the top surface of the gate insulating layer (114/138) and a bottom
surface of the capping layer (148) are substantially coplanar (See Fig 1B).
Regarding Claim 13, Cheng disclose: The semiconductor device of
claim 1, The limitation " wherein the conductive pillar is formed by a first etching process and a second etching process following the first etching process." in claim 13 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product "gleaned" from the process steps, which must be determined in a "product by process" claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in "product by process" claim or not.
Regarding Claim 14, Cheng discloses: The semiconductor device of
claim 1, The limitation " wherein the landing pad is formed by a first etching process." in claim 13 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product "gleaned" from the process steps, which must be determined in a "product by process" claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in "product by process" claim or not.
Claim(s) 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Huang-Nan (US 2020/0312707 A1 hereinafter Chen).
Regarding Claim 16, Chen discloses in Fig 1 – 2N: A semiconductor device, comprising:
a substrate (100);
a word line (202) disposed in the substrate;
a dielectric liner (206a/b) disposed between the substrate and the word line and surrounding the word line (See Fig 2N);
an insulative plug (208a/b) disposed in the substrate (100) and extending into the word line;
a void (AG) extending around a perimeter of the insulative plug (208a/b); and
an impurity region (AA) disposed in the substrate and on either side of the word line, wherein the impurity region serves as a source/drain region of a recessed access device (RAD) transistor [0027-0042].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Uno et al (US 2013/0207171A1 hereinafter Uno).
Regarding Claim 15, Cheng discloses: The semiconductor device of claim 1.
Cheng does not disclose: a bit line contact disposed on the substrate and adjacent to the contact structure; a capacitor plug disposed on the landing pad and electrically connected to the landing pad; and a storage capacitor disposed on the capacitor plug and electrically connected to the capacitor plug; wherein the bit line contacts is shorter than the contact structure that a top end of the bit line contact is lower than a top end of the capacitor contact.
However, Uno in a similar device teaches in Fig 10: a bit line contact (104A) disposed on the substrate and adjacent to the contact structure (109/108); a capacitor plug (lower layer of 113 – see [0140] disposed on the landing pad and electrically connected to the landing pad; and a storage capacitor (Cap) disposed on the capacitor plug and electrically connected to the capacitor plug (lower layer of 113) ; wherein the bit line contacts is shorter than the contact structure (See Fig 10) that a top end of the bit line contact is lower than a top end of the capacitor contact (See Fig 10) [0130-0138].
References Cheng and Uno are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Cheng with the specified features of Uno because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Cheng and Uno so that a bit line contact disposed on the substrate and adjacent to the contact structure; a capacitor plug disposed on the landing pad and electrically connected to the landing pad; and a storage capacitor disposed on the capacitor plug and electrically connected to the capacitor plug; wherein the bit line contacts is shorter than the contact structure that a top end of the bit line contact is lower than a top end of the capacitor contact as taught by Uno in Cheng’s device since, this provides a high-performance DRAM having an excellent data holding characteristic can be readily formed even when the capacitor elements are arranged in a highly integrated (miniaturized) manner [0144].
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Karda et al (US 2023/0361118 A1 hereinafter Karda).
Regarding Claim 18, Chen discloses in Fig 1-2N: The semiconductor device of claim 16.
Chen does not specifically disclose: wherein the word line is made of germanium.
However, Karda in a similar device teaches in [0083]: wherein the word line is made of germanium.
References Chen and Karda are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Chen with the specified features of Karda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Karda so that the word line is made of germanium as taught by Karda in Chen’s device since, doped Ge is one of the commonly used conductor materials in semiconductor arts.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Huang (US 2024/0222370 A1 hereinafter Huang).
Regarding Claim 8, Cheng discloses in Fig 10: The semiconductor device of claim 7.
Cheng does not specifically disclose: wherein the liner layer is formed of a material including sp² hybridized carbon atoms.
However, Huang in a similar device teaches in [0053]: wherein the liner layer is formed of a material including sp² hybridized carbon atoms.
References Cheng and Huang are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Cheng with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Cheng and Huang so that the liner layer is formed of a material including sp² hybridized carbon atoms as taught by Huang in Cheng’s device since, this improves the performance of the peripheral gate structure [0008].
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sung (US 10,170,484 B1 hereinafter Sung).
Regarding Claim 19, Chen discloses in Fig 1-2N: The semiconductor device of claim 18.
Chen does not specifically disclose: wherein the isolation layer is made of germanium oxide.
However, Sung in a similar device teaches in claim 18 wherein the isolation layer is made of germanium oxide.
References Chen and Sung are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Chen with the specified features of Sung because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Sung so that the liner layer is formed of a material including sp² hybridized carbon atoms as taught by Sung in Chen’s device since, this improves the electrical isolation needed for the memory device to operate normally.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 17, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “further comprising: an isolation layer disposed in the substrate and employed to cap the word line; and a diffusion barrier liner disposed between the dielectric liner and the word line; wherein the void is buried in the isolation layer at a position that the void separates at least a portion of the word line from the isolation layer” as recited in claim 17 in combination with the remaining features.
The most relevant prior art references, Cheng, Chen and Uno, substantially teach the limitations of the claim 17, except for the limitations described in the preceding paragraph. None of the references disclose a void buried in the isolation layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM.
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811
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