Prosecution Insights
Last updated: October 01, 2026
Application No. 18/599,586

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §102§103§112
Filed
Mar 08, 2024
Priority
Mar 16, 2023 — JP 2023-042220
Examiner
DYKES, LAURA M
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
349 granted / 528 resolved
-1.9% vs TC avg
Strong +27% interview lift
Without
With
+26.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
34 currently pending
Career history
554
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.8%
+16.8% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 528 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This OA is in response to the claims filled on 3/8/2024 that has been entered, wherein claims 1-14 are pending. Election/Restrictions Applicant’s election without traverse of Invention I, claims 1-10 in the reply filed on 8/4/2026 is acknowledged. Claims 11-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/8/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the first conductive layer" in line 17. There is insufficient antecedent basis for this limitation in the claim. Is the first conductive layer one of the plurality of first conductive layers of line 7 or distinct layer different from the plurality of first conductive layers? For the purpose of examination “the first conductive layer” will be interpreted as “a first conductive layer of the plurality of first conductive layers”. Claims 2-10 depend on claim 1 and inherit it deficiencies. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rabkin et al. (US 2022/0208748 A1) as cited in the IDS of 3/8/2024. Regarding claim 1, Rabkin teaches a semiconductor device(Fig. 27) comprising: a first chip(700, ¶0238) including a peripheral circuit(710, ¶0238); and a second chip(1000, ¶0238) including an array structure of memory cell transistors and bonded to the first chip(700, ¶0238), wherein the second chip(1000, ¶0238) includes a stacked body(32, 46, ¶0238) including a memory part and a staircase part, the memory part including a plurality of first conductive layers(46, ¶0238) and a plurality of first insulating layers(32, ¶0238) alternately stacked in a first direction, the staircase part being a part at which end parts of the plurality of first conductive layers(46, ¶0238) are formed in a stepped shape(¶0238), a contact(86/186, ¶0114) connected to the staircase part, a first column-shaped part(58, ¶0238) formed to extend through the memory part in the first direction and forming a memory cell transistor(¶0095, ¶0110) at an intersection part with a first conductive layer(46, ¶0238) of the plurality of first conductive layers(46, ¶0238), a second conductive layer(240, ¶0203, ¶0239) formed above the stacked body(32, 46, ¶0238) and connected to an upper end part of the first column-shaped part(58, ¶0238), and a second column-shaped part(20, ¶0096) formed to extend through the staircase part in the first direction, and the second column-shaped part(20, ¶0096) is electrically insulated from the second conductive layer(240, ¶0203, ¶0239). Regarding claim 2, Rabkin teaches the semiconductor device according to claim 1, wherein the second conductive layer(240, ¶0203, ¶0239) contains a metallic material(¶0202). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 2022/0208748 A1) as cited in the IDS of 3/8/2024 in view Li et al. (US 2018/0121345 A1) . Regarding claim 3, Rabkin teaches the semiconductor device according to claim 2, wherein the first column-shaped part(58, ¶0238) includes a first core part(62, ¶0090) formed to extend in the first direction and formed of an insulator(¶0090), a semiconductor layer(60, ¶0089,¶0093) provided between the first core part(62, ¶0090) and the first conductive layer(46, ¶0238), and an electric charge accumulation film(54, ¶0085) provided between the semiconductor layer(60, ¶0089,¶0093) and the first conductive layer(46, ¶0238), and the semiconductor layer(60, ¶0089,¶0093) and the second conductive layer(240, ¶0203, ¶0239) are joined with each other(¶0202). Rabkin does not explicitly state the semiconductor layer(60, ¶0089,¶0093) and the second conductive layer(240, ¶0203, ¶0239) are Schottky-joined with each other(¶0202). Li teaches a semiconductor device(Fig. 2L1) wherein the semiconductor layer(214, ¶0072) and the second conductive layer(201, ¶0075) are Schottky-joined with each other(¶0075). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rabkin, so that the semiconductor layer and the second conductive layer are Schottky-joined with each other, as taught by Li, in order to have leakage current control in the semiconductor layer(¶0079). Regarding claim 4, Rabkin teaches the semiconductor device according to claim 3, wherein the second column-shaped part(20, ¶0096) has a same structure(¶0095) as the first column-shaped part(58, ¶0238). Regarding claim 5, Rabkin teaches the semiconductor device according to claim 4, wherein the second conductive layer(240, ¶0203, ¶0239) is formed at a part above the stacked body(32, 46, ¶0238) except for a part above the second column-shaped part(20, ¶0096), and an upper end part of the second column-shaped part(20, ¶0096) is spaced apart from the second conductive layer(240, ¶0203, ¶0239) and electrically insulated from the second conductive layer(240, ¶0203, ¶0239). Regarding claim 6, Rabkin teaches the semiconductor device according to claim 5, further comprising: a second insulating layer(230,¶0239) formed above the second conductive layer(240, ¶0203, ¶0239); and a fourth conductive layer(316,¶0243) formed above the second insulating layer(230,¶0239), wherein the upper end part of the second column-shaped part(20, ¶0096) is in contact with the second insulating layer(230,¶0239). Regarding claim 7, Rabkin teaches the semiconductor device according to claim 6, wherein an upper end part of at least one of the semiconductor layer(60, ¶0089,¶0093) and the electric charge accumulation film(54, ¶0085) of the second column-shaped part(20, ¶0096) is in contact with the second insulating layer(230,¶0239). Regarding claim 8, Rabkin teaches the semiconductor device according to claim 6, wherein part of the second conductive layer(240, ¶0203, ¶0239) is provided between an upper end part of the first core part(62, ¶0090) and the second insulating layer(230,¶0239). Regarding claim 9, Rabkin teaches the semiconductor device according to claim 6, wherein the second conductive layer(240, ¶0203, ¶0239) is not provided between an upper end part of the first core part(62, ¶0090) [of the second column-shaped part(20, ¶0096)] and the second insulating layer(230,¶0239). Regarding claim 10, Rabkin teaches the semiconductor device according to claim 3, wherein the second column-shaped part(20, ¶0096) includes a second core part(62 of 20, ¶0090) formed to extend in the first direction, and an insulating film(52, ¶0084 provided between the first conductive layer(46, ¶0238) and the second core part(62 of 20, ¶0090). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al. (US 2022/0352091 A1) Discloses a semiconductor device. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M DYKES/Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Mar 08, 2024
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740055
SEMICONDUCTOR DEVICE
2y 9m to grant Granted Sep 15, 2026
Patent 12733516
SEMICONDUCTOR PACKAGE WITH EXPOSED ELECTRICAL CONTACTS
3y 8m to grant Granted Sep 08, 2026
Patent 12713704
SEMICONDUCTOR DEVICE AND ESD PROTECTION DEVICE COMPRISING THE SAME
4y 0m to grant Granted Aug 18, 2026
Patent 12701872
ARRAY SUBSTRATE, HAVING AN ISOLATON PILLAR IN A HOLE BORDER AREA, PREPARATION METHOD THEREOF AND DISPLAY DEVICE
4y 11m to grant Granted Aug 04, 2026
Patent 12701715
SEMICONDUCTOR MEMORY DEVICE
2y 9m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
93%
With Interview (+26.9%)
2y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 528 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month