Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted has been accepted by the examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1 recites “a side of the first region along a first direction” and “a first side of the second stack along a second direction, the second direction being perpendicular to the first direction” but these directions are not clearly shown in the drawings
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim (US # 20210028184).
Regarding Claim 15, Kim (US # 20210028184) teaches a method for forming a three-dimensional (3D) memory device (see Figs. 1 and 3 and corresponding text), comprising:
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forming a semiconductor layer (STS);
forming a first stack (GST) on one side (top side) of the semiconductor layer and in a first region (AR1) of the 3D memory device, wherein the first stack comprises layer pairs each comprising a conductive layer (CP1 to CPn) and a first dielectric layer (ILD); and
forming capacitors comprising first contacts (CE) disposed in a second region (AR2) of the 3D memory device, wherein the second region is disposed on a side (right side) of the first region along a first direction (D3, according to Fig. 1).
Regarding Claim 16, Kim (US # 20210028184) teaches the method of claim 15, wherein the second region is at an edge (AR2 is at the periphery of the 3D memory) of the 3D memory device in which contact pads (contacts L1, L2 are above electrodes CE in the AR2 region) of the 3D memory device are disposed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20210028184) in view of Nishikawa (US # 10629675).
Regarding Claim 1, Kim (US # 20210028184) teaches a method for forming a three-dimensional (3D) memory device (10), comprising:
forming a stack (ST1; especially see Fig. 3), the stack comprising a first region (AR1) and a second region (AR2) disposed on a side (laterally beside AR1) of the first region along a first direction (direction D3, as shown in Fig. 1), the stack comprising a first stack (GST) in the first region and a second stack (DST) in the second region (shown especially see Fig. 3);
forming an interlayer dielectric layer (UI1 and UI2) over the second stack (shown); and
forming capacitors comprising first contacts (CE) each extending through the dielectric stack DST (and penetrating into LCA) and disposed on a first side (CE extends from the top side of DST and then down to LCA) of the second stack along a second direction (D2), the second direction being perpendicular to the first direction (D2 and D3 are perpendicular and lie on the plane of the main substrate surface, as shown in Fig. 1).
Although Kim discloses much of the claimed invention, it does not explicitly teach the first contacts extending through the ILD layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
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For example, Nishikawa is in the same or analogous field, and it teaches capacitors comprising first contacts (992, 994, 996) each extending through a retro-stair-stepped ILD layer (165, 265).
A person having ordinary skill in the art would have recognized that modifying the capacitor isolation of Kim with the capacitor suggested by Nishikawa would be obvious. Specifically, the modification suggested by Nishikawa would be to employ a method comprising forming first contacts extending through the ILD layer. The rationale for this obvious modification is that highly-homogenous dielectric fill material avoids etch-selectivity challenges, thus this would improve dimensional uniformity (col. 13, lns. 57-65; col. 14, 11; col. 39-40; see also Figs. 33A-33H).
Regarding Claim 2, Kim teaches the method of claim 1, wherein forming a stack comprises:
forming the stack comprising layer pairs each comprising a first dielectric layer (111) and a second dielectric layer (113) different from the first dielectric layer (see [0064, 67]); and
etching the stack to form the first stack comprising a gate stack structure (GST) in the first region (AR1; sacrificial layers are etched away and replaced with conductive materials; see Fig. 6A, 6B), leaving at least one layer pair to form the second stack in the second region (see pairs of sacrificial layers 113 and 121, and insulating layers 111, 123 over 100b).
Although Kim discloses much of the claimed invention, it does not explicitly teach the method step detail of etching the stack to form the first stack comprising a staircase structure in the first region.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
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For example, Nishikawa is in the same or analogous field, and it teaches a method step (shown best in Fig. 3 and see also col. 13) detail of etching a stack to form a first stack comprising a staircase structure (iteratively trimming a mask layer and vertically recessing the alternating stack of 132, 142) in a first region (200; the capacitor region 900 is also masked).
A person having ordinary skill in the art would have recognized that modifying the AR1 region of Kim with the staircase feature suggested by Nishikawa would be obvious. Specifically, the modification suggested by Nishikawa would be to employ a method step detail of etching the stack to form the first stack comprising a staircase structure in the first region. The rationale for this obvious modification is that staircase features provide a standard mechanism for exposing word lines and control gate connection (see col. 10). This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of a 3D memory with a staircase are well known in the art (see MPEP 2144.01).
Regarding Claim 3, Nishikawa, as applied to claim 2, teaches the method of claim 2, wherein etching the stack comprises: patterning a trim-etch mask on the stack (col. 29, lns. 29-57); and performing, using the trim-etch mask, a first number of trim-etch cycles in the first region of the stack to form the first stack, and a second number of trim-etch cycles in the second region of the stack (the capacitor area 900 is masked without being trimmed, so it has zero trim cyles).
Regarding Claim 4, Nishikawa, as applied to claim 3, teaches the method of claim 3, wherein the first number is greater than the second number (the trim number first number is equal to the number of steps on the stairs, which is necessarily greater than zero).
Regarding Claim 5, Kim in view of Nishikawa teaches the method of claim 2, wherein the first stack comprises first layer pairs each comprising a portion of the first dielectric layer and a portion of the second dielectric layer in the first region (Nishikawa modifies the GST of Kim such that it retains ILD at each level and also portions of sacrificial layers beyond where the conductor CP1 extends at each level of the staircases), and the second stack comprises the at least one layer pair comprising a portion of the first dielectric layer and a portion of the second dielectric layer in the second region (DST has multiple pairs that have at least a portion remaining of the dielectric layers (SA1-San and ILD’) in the AR2 stack).
Regarding Claim 6, Kim teaches the method of claim 5, further comprising replacing the second dielectric layers of the first stack with conductive layers in the first region (see Fig. 6A-6B and corresponding text describing the replacement process in AR1).
Regarding Claim 7, Nishikawa, as applied to claim 6, teaches the method of claim 6, further comprising forming second contacts (vertical contact via structures are shown in Fig. 19A) corresponding to conductive layers (horizontal layers 146, 246, 242) on the staircase structure.
Regarding Claim 8, Nishikawa, as applied to claim 6, renders obvious the method of claim 7, wherein the second contacts and first contacts are formed by the same process (see reasons below).
Nishikawa teaches that dissimilar via-types are etched concurrently and filled concurrently by the same process steps (holes 129, 149, 169 formed concurrently, Figs. 4A-4B; contacts 86, 88, and capacitor contacts formed concurrently, Figs. 21A-21B).
A person having ordinary skill in the art would have recognized that modifying the etch/fill steps of Nishikawa with the concurrency suggested throughout would be obvious. Specifically, the modification suggested by Nishikawa’s concurrency would be to employ a method of claim 7, wherein the second contacts and first contacts are formed by the same process. The rationale for this obvious modification is that concurrent formation provides efficiency. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of concurrent etch/fill steps are well known in the art (see MPEP 2144.01).
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Regarding Claim 9, Nishikawa, as applied to claim 2, teaches the method of claim 2, further comprising forming the ILD layer (165, 265) on the staircase structure and between the first stack and the second stack (it extends to both regions).
Regarding Claim 10, Nishikawa, as applied to claim 2, teaches the method of claim 1, wherein a thickness of the ILD layer is equal to or greater than a thickness of the first stack (the ILD layers of Nishikawa 165 and 265 are a bit thicker than the first stack (i.e. WL stack)).
Regarding Claim 11, Kim teaches the method of claim 1, further comprising forming an interconnect layer (UI1 and UI2) connecting with the first contacts CCT1) and over the ILD layer (shown in Fig. 3 of Kim).
Regarding Claim 12, Kim teaches the method of claim 1, further comprising forming a semiconductor layer (LCA) disposed on a second side (bottom side, as shown in Fig. 3) of the second stack, the second side being opposite to the first side (top vs. bottom).
Regarding Claim 13, Kim teaches the method of claim 1, wherein the first contacts extend along a third direction (D1 is vertical, as shown in Fig. 3) perpendicular to the first direction and the second direction (axis symbols are shown in Fig. 1).
Regarding Claim 14, Kim teaches the method of claim 1, wherein the first contacts include a conductive material ([0048-49]).
Regarding Claim 17, Kim in view of Nishikawa was already established in the rejection of claim 1, and that essential reasoning renders this claim limitation obvious.
Regarding Claim 20, Kim in view of Nishikawa was already established in the rejection of claim 13, and that essential reasoning renders this claim limitation obvious.
Claim 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20210028184) in view of Nishikawa (US # 10629675) and further in view of Fastow (20190043836).
Regarding Claim 18, although Kim in view of Nishikawa discloses much of the claimed invention, it does not explicitly teach the limitations of claim 18.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Fastow is in the same or analogous field, and it teaches the method of claim 15 (FIG. 1A illustrates a cross section of an example of a 3D flash storage component with shared CMOS circuitry formed using wafer bonding), further comprising: forming peripheral circuits (CMOS peripheral circuitry); forming a bonding interface (242) between the peripheral circuits and the first stack (3D NAND memory array die 203B); and bonding the peripheral circuits and the first stack through the bonding interface (shown).
A person having ordinary skill in the art would have recognized that modifying the device of Kim in view of Nishikawa with the bonding architecture suggested by Fastow would be obvious. Specifically, the modification suggested by Fastow would be to employ a method of claim 15, further comprising: forming peripheral circuits; forming a bonding interface between the peripheral circuits and the first stack; and bonding the peripheral circuits and the first stack through the bonding interface. The rationale for this obvious modification is that this bonding architecture provides reduced peripheral overhead area and enables sharing of a single die across multiple memory array dies. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of bonded peripheral circuits are well known in the art (see MPEP 2144.01).
Regarding Claim 19, Fastow, as applied to claim 18, teaches the method of claim 18, wherein the first contacts are connected to at least one of the peripheral circuits (the memory array is necessarily connected to the CMOS circuitry).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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