DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5 – 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chujo (US 2008/0083558 A1) in view of Hwang (US 2022/0071016 A1) and Harazono (US 2018/0146558 A1).
Regarding Claim 1, Chujo (US 2008/0083558 A1) discloses a wiring substrate (Fig 1,5-7), comprising: a glass substrate (2; [0068] “glass”) and a through-hole conductor (4,8; [0072]) formed in the glass substrate (2); a resin insulating layer (11; [0074]) formed on a surface (upper surface of 2) of the glass substrate (2) and comprising resin ([0074] “resin”); a conductor layer (e.g. layer with 12a on the left side of Fig 1) formed on a surface (e.g. upper surface of 11a) of the resin insulating layer (11) and comprising a seed layer (12’a; [0093-0095]; “seed”) and an (electrolytic plating) layer (12a; [0093-0095] “Electroplating”) formed on the seed layer (12’a); and a via conductor (e.g. central 13a in Fig 1) formed in the resin insulating layer (11) such that the via conductor (central 13a) is electrically connected ([0005,0011,0023,0051]) to the through-hole conductor (4,8) formed in the glass substrate (2) and includes the seed layer (12’a; [0093-0095]) and (electrolytic plating) layer (13a; [0093-0095]) extending from the conductor layer (12a), wherein the conductor layer (12a) and the via conductor (13a) are formed such that the seed layer (12’a) (is formed by sputtering ([0093])), and the resin insulating layer (11a) has an opening (see Fig 6 showing a hole in 11a) in which the via conductor (13a) is formed.
Chujo does not disclose a resin insulating layer comprising resin and inorganic particles and the resin insulating layer has an opening in which the via conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the resin insulating layer and that the inner wall surface in the opening is substantially a common surface formed of flat parts of the first particles and a flat surface of the resin.
Hwang (US 2022/0071016 A1) teaches of a printed wiring board (Fig 13-16), comprising: a first conductor layer (330); a resin insulating layer (310) formed on the first conductor layer (320) having an opening (VH1,VH2); a second conductor layer (320) formed on a surface (upper surface of 310) of the resin insulating layer (310) and comprising a seed layer (340) and an (electrolytic plating) layer (350) formed on the seed layer; and a via conductor (340,350 at VH) formed in the opening (VH1) of the resin insulating layer (310) and comprising the seed layer (340) and the (electrolytic plating) layer (350) formed on the seed layer such that the via conductor is connecting the first conductor layer (330) and the second conductor layer (320), and the resin insulating layer (310) comprising resin (311) and inorganic particles (312; [0071]) and the resin insulating layer (310) has an opening (VH) in which the via conductor is formed such that the inorganic particles (312) include first particles (312 shown as a partial sphere or circle at the edge or surface of VH1,VH2) forming an inner wall surface in the opening and second particles (312 shown as a whole sphere or circle away from VH1) embedded in the resin insulating layer (311) and that the inner wall surface in the opening is formed of flat parts (flat surface of 312 at VH) of the first particles (312) and a flat surface (a flat surface of 312 is shown in Fig) of the resin (311).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Chujo, wherein a resin insulating layer comprising resin and inorganic particles and the resin insulating layer has an opening in which the via conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the resin insulating layer and that the inner wall surface in the opening is formed of flat parts of the first particles and a flat surface of the resin as taught by Hwang, in order to control dielectric constant, provide rigidity, prevent cracks, provide a desired roughened surface, improve peel strength, and improve product reliability (Hwang, [0036,0072-0076,0144]).
Harazono (US 2018/0146558 A1) teaches of a wiring substrate (Fig 1-2), comprising: a substrate (1) and a through-hole conductor (6) formed in the substrate (1); a resin insulating layer (2) formed on a surface (upper surface of 1) of the substrate (1) and comprising resin (7; [0012] “resin”) and inorganic particles ([0012]); and the resin insulating layer (2) has an opening (10; opening in 2 for 3) in which the conductor (3) is formed such that the inorganic particles (8) include first particles (8 at the wall 10a of 3) forming an inner wall surface (10a; inner wall of 3) in the opening and second particles (8 away from 3) embedded in the resin insulating layer (7) and that the inner wall surface (10a) in the opening (10) is substantially a common surface formed of flat parts ([0013,0016,0018,0020]) of the first particles (8) and a flat surface ([0013,0016,0018,0020]) of the resin (7).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Chujo in view of Hwang, wherein the resin insulating layer comprising resin and inorganic particles and the resin insulating layer has an opening in which the conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the resin insulating layer and that the inner wall surface in the opening is substantially a common surface formed of flat parts of the first particles and a flat surface of the resinas taught by Harazono, in order to ensure a path allowing high frequency signal to propagate efficiently, provide good transmission characteristics, prevent difficulties in efficiently transmitting signal, and deal with skin effect (Harazono, [0003,0013,0016,0018-0021]), such that the combination of Chujo in view of Hwang and Harazono would teach a resin insulating layer comprising resin and inorganic particles and the resin insulating layer has an opening in which the via conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the resin insulating layer and that the inner wall surface in the opening is substantially a common surface formed of flat parts of the first particles and a flat surface of the resin.
The Claim states a “electrolytic plating” and “is formed by sputtering” but “electrolytic plating” and “is formed by sputtering” does not represent product structure but only refers to the process by which the layers are formed. Thus the Claim is a product claim that recites a process step(s) of electrolytic plating and sputtering, and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 5, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Hwang further teaches the wiring substrate (Fig 13-16) according to claim 1, wherein the resin insulating layer (310) is formed such that the flat parts (flat regions or portions as seen in Fig 14; note that the claim has not structurally limited this claimed “parts”) of the first particles (312) have exposed surfaces (about VH2) forming steps (for example a surface of cut 312 at upper region of VH is away from the wall surface of VH1 and thus is forming a step-like region in Fig 14) between the exposed surfaces (VH2) and the flat surface (VH1) of the resin.
Regarding Claim 6, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Hwang further teaches the wiring substrate (Fig 13-16) according to claim 1, wherein the resin insulating layer (310) is formed such that each of the second particles (312 shown as a whole sphere or circle away from VH1) has a spherical shape (see Fig 13-16 and [0023] defining a diameter).
Regarding Claim 7, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Hwang further teaches the wiring substrate (Fig 13-16) according to claim 1, wherein the resin insulating layer (310) is formed such that each of the first particles (312) has a shape (obtained by cutting a sphere (see 312 away form VH as spherical; [0023] defining a diameter) along a flat surface).
The Claim states a “obtained by cutting a sphere along a flat surface” but “obtained by cutting a sphere along a flat surface” does not represent product structure but only refers to the process by which the surface is formed. Thus the Claim is a product claim that recites a process step(s) of cutting and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 8, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Hwang further teaches the wiring substrate (Fig 13-16) according to claim 6, wherein the resin insulating layer (310) is formed such that the first particles (312) have shapes (obtained by cutting the second particles (312) along a flat surface).
The Claim states a “obtained by cutting the second particles along a flat surface” but “obtained by cutting the second particles along a flat surface” does not represent product structure but only refers to the process by which the surface is formed. Thus the Claim is a product claim that recites a process step(s) of cutting and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 21, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Harazono further teaches the wiring substrate (Fig 1-2) according to claim 1, wherein the resin insulating layer (2) is formed such that the common surface formed of the flat parts of the first particles (8) and the flat surface of the resin (7) is a flat surface ([0003,0013,0016,0018-0021] “grooves 10 filled with the wiring conductors 3 are constituted by flat surfaces in which the cross-section of the insulating resin 7 and the cross-sections of the inorganic insulating particles 8 are exposed in flush with each other”).
Claim(s) 9 – 18, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chujo (US 2008/0083558 A1) in view of Hwang (US 2022/0071016 A1) and Harazono (US 2018/0146558 A1) as applied to claims 1 and 6 and 21 above and further in view of Lin (US 2012/0043127 A1).
Regarding Claims 9 and 14 and 22, Chujo in view of Hwang and Harazono teaches the limitations of the preceding claim and Chujo further discloses the wiring substrate (Fig 1) according to claims 1 and 6 and 21, wherein the conductor layer (12) and the via conductor (13) are formed such that the seed layer ([0093]) includes copper ([0093]).
Chujo does not disclose an alloy comprising copper, aluminum and at least one metal selected from the group consisting of nickel, zinc, gallium, silicon, and magnesium.
Lin (US 2012/0043127 A1) teaches of a wiring substrate (Fig 3), wherein a conductor layer (220) and a via conductor (230) are formed such that a seed layer ([0022]) includes an alloy comprising copper ([0022]), aluminum ([0022]), and at least one metal selected from the group consisting of nickel ([0022]), zinc, gallium, silicon ([0022]), and magnesium.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Chujo in view of Hwang and Harazono, comprising an alloy comprising copper, aluminum at least one metal selected from the group consisting of nickel, zinc, gallium, silicon, and magnesium as taught by Lin, in order to facilitates the nucleation and growing of subsequent metal layers formed by the electro plating process (Lin, [0022]) and furthermore since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 9 lines 8-25, Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claims 10 and 15 and 23, Chujo in view of Hwang, Harazono and Lin teaches the limitations of the preceding claim and Lin further teaches the wiring substrate (Fig 3) according to claims 9 and 14 and 22, wherein the seed layer in the conductor layer and the via conductor is formed such that the at least one metal in the alloy includes silicon ([0022]).
Regarding Claims 11 and 16, Chujo in view of Hwang, Harazono and Lin teaches the limitations of the preceding claim.
Chujo does not disclose the wiring substrate according to claims 9 and 10, wherein the seed layer in the conductor layer and the via conductor is formed such that a content of aluminum in the alloy is in a range of 1.0 at % to 15.0 at %.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Chujo in view of Hwang, Harazono and Lin, wherein the seed layer in the conductor layer and the via conductor is formed such that a content of aluminum in the alloy is in a range of 1.0 at % to 15.0 at %, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, and in order to facilitates the nucleation and growing of subsequent metal layers. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 9 lines 8-25, Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claims 12 and 17, Chujo in view of Hwang, Harazono and Lin teaches the limitations of the preceding claim.
Chujo does not disclose the wiring substrate according to claims 9 and 10, wherein the seed layer in the conductor layer and the via conductor is formed such that the alloy includes carbon and that a content of carbon in the alloy is 50 ppm or less.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Chujo in view of Hwang, Harazono and Lin, wherein the seed layer in the conductor layer and the via conductor is formed such that the alloy includes carbon and that a content of carbon in the alloy is 50 ppm or less, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice and in order to facilitates the nucleation and growing of subsequent metal layers. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 9 lines 8-25, Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claims 13 and 18, Chujo in view of Hwang, Harazono and Lin teaches the limitations of the preceding claim.
Chujo does not disclose the wiring substrate according to claims 9 and 10, wherein the seed layer in the conductor layer and the via conductor is formed such that the alloy includes oxygen and that a content of oxygen in the alloy is 100 ppm or less.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Chujo in view of Hwang, Harazono and Lin, wherein the seed layer in the conductor layer and the via conductor is formed such that the alloy includes oxygen and that a content of oxygen in the alloy is 100 ppm or less, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice and in order to facilitates the nucleation and growing of subsequent metal layers. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 9 lines 8-25, Applicant has not disclosed any criticality for the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
Prosecution Insights