Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I, Subspecies B Subspecies ii in the reply filed on 08/11/2026 is acknowledged.
Claim8 and 12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventio, species and/or subspecies, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/11/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims, 5, 10 and 11 the claims recite “do not differ from each other by more than 20% or 10% or 5%”, “equal to or greater than 20 A, 40 A, 60 A, 70 A, or 80 A”, and “equal to or greater than 200 V, 400 V, 600 V, 800 V, 1 kV, or 1.2 kV” so that it is unclear what values are required for the purpose of examination the claims will be given the interpretation “do not differ from each other by more than 20%”, “equal to or greater than 20 A”, and “equal to or greater than 200 V” so that the claims are given their broadest interpretation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7 and 9-11 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Grassman (US 20230025736 A1).
Regarding claim 1, Grassman teaches in Figs. 1-2 with associated text a power transistor chip package, comprising: a power transistor chip 106 comprising a first load electrode (second load terminal [0038]) on a first side (lower surface [0038]) (Figs. 1-2B, [0038]), a second load electrode (first load terminal [0038]) on a second side (upper surface [0038]) opposite the first side, and a control electrode (control electrode [0038]) (Figs. 1-2B, [0038]); a chip pad 102 on which the power transistor chip is disposed, the first side facing the chip pad and the first load electrode being electrically connected to the chip pad (Figs. 1-2B, [0038]-[0039]); an encapsulation body 110 encapsulating the power transistor chip (Figs. 1-2B, [0036]), the encapsulation body comprising a footprint side (either side could be considered the footprint side Fig. 2B), a top side opposite the footprint side, and side faces extending between the footprint side and the top side (Fig. 2B); a first package load terminal (exposed surface of 102 [0039]) electrically connected to the first load electrode of the power transistor chip (Figs. 1 and 2B, [0039]); part I and part II second package load terminals (at least two of the leads 112 on different sides of package and parts of 108 connecting them) both electrically connected directly to the second load electrode of the power transistor chip (Figs. 1 and 2A, [0039]); and a package control terminal electrically 114 connected to the control electrode of the power transistor chip (Figs. 1 and 2B, [0039]), wherein the part I and the part II second package load terminals are aligned with opposite sides faces of the encapsulation body (Fig 2A, [0040]).
Regarding claim 2, Grassman teaches the first package load terminal is disposed at the top side of the encapsulation body (here the top side is considered to be the side opposite to that at which 102 is exposed).
Regarding claim 3, Grassman teaches the first package load terminal is disposed at the footprint side of the encapsulation body (here the top side is interpreted to be the side at which 102 is exposed).
Regarding claim 4, Grassman teaches an electrical interconnect 108 configured to connect the second load electrode to the part I and the part II second package load terminals, wherein the electrical interconnect comprises at least a bond wire or a ribbon or a clip (Fig. 2A, [0035] and [0039]).
Regarding claim 6, Grassman teaches an additional package control terminal (114 on other side than the terminal 114 interpreted to be the package control terminal), wherein the package control terminal and the additional package control terminal are aligned with the opposite sides faces of the encapsulation body (Figs. 1 and 2B).
Regarding claim 7, Grassman teaches a package sense terminal and an additional package sense terminal (further terminals 104 used as sense terminal not shown but described in [0039]) aligned with the opposite sides faces of the encapsulation body ([0039]).
Regarding claim 9, Grassman teaches the part I and the part II second package load terminals are each formed of a plurality of gull wing leads (Fig. 2A).
Regarding claim 10, Grassman teaches a maximum load current of the power transistor chip package is equal to or greater than 20 A, 40 A, 60 A, 70 A, or 80 A (100 A or more [0037]).
Regarding claim 11, Grassman teaches the power transistor chip package is configured for switching voltages equal to or greater than 200 V, 400 V, 600 V, 800 V, 1 kV, or 1.2 kV (1200 V or 1,2 kV [0037]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Grassman as applied to claim 1 and further in view of Nakamura (US 20190109077 A1 hereinafter Nakamura).
Regarding claim 5, Grassman teaches the power transistor chip package of claim 4, wherein the electrical interconnect comprises: a part I electrical interconnect (part of 108 on one side of the die to 112 on that side) connecting the second load electrode to the part I second package load terminal; and a part II electrical interconnect (part of 108 on one side of the die to 112 on that side) connecting the second load electrode to the part II second package load terminal (Figs. 1 and 2A).
Grassman does not specify the electrical resistance of the part I electrical interconnect and the electrical resistance of the part II electrical interconnect do not differ from each other by more than 20% or 10% or 5%, however Grassman show in Fig1 for example that the part I electrical interconnect and the the part II electrical interconnect have a similar structure and while they are not symmetric in the disclosed embodiments Grassman discloses a power switching device package may comprise any number of discrete transistor devices [0037] so that in a case where a single or an odd number of transistor devices were in a line the part I electrical interconnect and the the part II electrical interconnect would be substantially symmetric.
Nakamura discloses in Figs. 7-8 with associated text wirings 107a, 107b, 109a and 109b similar to the part I electrical interconnect and the part II electrical interconnect of Grassman that have equal resistances and therefore do not differ from each other by more than 20% or 10% or 5%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the electrical resistance of the part I electrical interconnect and the electrical resistance of the part II electrical interconnect do not differ from each other by more than 20% or 10% or 5% because, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to make the electrical resistance of the part I electrical interconnect and the electrical resistance of the part II electrical interconnect do not differ from each other by more than 20% or 10% or 5% with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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