DETAILED ACTION
This action is responsive to the amendments filed March 4, 2026. Claims 1-19 are pending. Claims 1, 3-13, and 15 have been amended. Claims 18 and 19 are new. Claims 1 and 9 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Claim Objections
The objection to claims 7 and 8 as substantially duplicate claims, as set forth in the previous Office action, has been considered. Applicant has persuasively pointed out that the claims are not duplicates because they differ in element four reciting when the erase operation has been performed. Accordingly, the objection has been withdrawn.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1 and 9, there are three distinct issues which make the claim unclear:
The final clause of each claim recites: “and in a case where the first circuit performs the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing and where the erase operation is suspended in a first period of the plurality of periods, after the erase operation is resumed, in the erase voltage applying operation, the erase execution period is started from the first period.” It is unclear what “a first period of the plurality of periods” and the subsequent “the first period” refer to. The phrase introduces “a first period” (indefinite article) without sufficient antecedent basis or definition that would allow one of ordinary skill in the art to determine with reasonable certainty whether “the first period” means (i) only the chronologically first period in the sequence of periods that comprise the erase execution period, or (ii) whichever arbitrary period in the sequence was interrupted by the suspension (as actually described in the specification of the instant application at [0152], where resumption occurs from the sixth period). The specification consistently uses “first period,” “second period,” …, “tenth period” as fixed sequential labels for the periods within pEW (see [0101] and FIG. 7). The claim language does not resolve this mismatch.
The overall structure of each claim is a single, excessively long run-on sentence containing multiple independent limitations joined by commas, “wherein” clauses, and “and” connectors. This format makes it impossible to ascertain the precise metes and bounds of the claimed invention, particularly how the timer-circuit limitation integrates with (or is required by) the voltage-based or suspension-count-based resumption decision and the conditional “first period” resumption rule.
The recitation in both claims— “the first circuit including a timer circuit, the timer circuit configured to measure a time during an erase execution period in which the erase voltage is applied in the erase voltage applying operation, wherein the erase execution period includes a plurality of periods”—fails to clearly define the functional relationship between the timer circuit and the remainder of the claimed operation. It is unclear whether the timer’s measurement of discrete periods is the mechanism that actually enables the “erase execution period is started from the first period” feature or whether the timer is merely present without any claimed connection to the resumption logic.
For purposes of compact prosecution (MPEP § 2173.06), the ambiguous "first period" language in the final clause will be interpreted to mean whichever period (of the plurality of periods) during which the suspension actually occurred. Under this interpretation, the erase execution operation resumes from the point it was interrupted (consistent with the specification).
Dependent claims 2-10, and 11-19 inherit the deficiencies of claims 1 and 9 and are similarly rejected.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 9-10, and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi et al. (US 2017026229; "Ochi" – of record) in view of Kim et al. (US 20230063656; "Kim").
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Regarding independent claim 1, notwithstanding the rejection for indefiniteness above, Ochi discloses a semiconductor memory device comprising:
a memory cell including a transistor (Fig. 4);
an interconnect (Fig. 5:58 CPWELL);
and a first circuit configured to perform an erase operation including (Fig. 2: 120 sequencer circuit)
an erase voltage applying operation of applying an erase voltage between a gate of the transistor and a channel of the transistor via the interconnect (para. 107; "The sequencer 120 raises the potential of the well interconnect CPWELL from voltage “VSS” to voltage “Vera1")
and an erase verify operation of determining a threshold voltage of the memory cell (Fig. 6. See also para. 125; "Specifically, at time instant “Ta11”, the sequencer 120 executes a first erase verify (Erase verify 1) operation"),
wherein the first circuit performs a first suspension processing of suspending the erase operation upon receiving a first command during the erase operation (para. 277; "Upon receiving the “FFh” command, the chip 100 immediately stops the operation which is currently executed (“Auto Suspend erase 1” operation)"),
and the first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 22 where it illustrates the sequencer applying Vera3 again after resuming suspended erase operation),
based on a voltage value of the interconnect at the time of receiving the first command (Fig. 22 where it illustrates the sequencer applying Vera3 prior to the erase operation. See also para. 279; "The chip 100 is configured to apply voltage “Vera3” to the well interconnect CPWELL during a predetermined period “Tera1_3”. However, in this embodiment, the chip 100 does not apply voltage “Vera3” to the well interconnect CPWELL during the predetermined period “Tera1_3”. Thus, when the chip 100 executes an “Auto Suspend erase 2”, the chip 100 re-applies the voltage “Vera3” to the well interconnect CPWELL during the predetermined period “Tera1_3", thereby demonstrating that the voltage after resuming is based on the voltage at the time of suspending the erase operation).
Ochi discloses resuming a suspended erase operation but is silent with respect to a timer circuit and the resuming of the erase operation where it was interrupted.
However, Kim teaches the first circuit including a timer circuit (Fig. 1A, Timer 144),
the timer circuit configured to measure a time during an erase execution period in which the erase voltage is applied in the erase voltage applying operation (para. 87; "The time duration being tracked by the timer can cumulatively grow across resuming the true erase sub-operation, and thus a total voltage ramping time"),
wherein the erase execution period includes a plurality of periods (Abstr. "The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse."),
and in a case where the first circuit performs the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing and where the erase operation is suspended in a first period of the plurality of periods, after the erase operation is resumed, in the erase voltage applying operation, the erase execution period is started from the first period (Fig. 6. step 640 Resume Erase. See also para 86; "At operation 640, the true erase sub-operation is resumed". It is noted that when a suspend command is executed during the erase, the timer is stopped (step 625). Upon resume (step 640) the timer is restarted. See also para. 87 "At operation 605, the timer is restarted. More specifically, the processing logic restarts the timer to be able to continue tracking the ramping period of the erase pulse at the memory line. The time duration being tracked by the timer can cumulatively grow across resuming the true erase sub-operation, and thus a total voltage ramping time." Thus, the resumption starts at the same place the erase operation left off which is analogous to the instant application.).
Ochi and Kim are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the erase suspension/resumption logic controlled by Ochi’s sequencer circuit with the timer-based tracking of discrete ramping periods and resumption from the interrupted point taught by Kim. Doing so would enable more efficient resumption of the erase voltage applying operation after suspension without unnecessary re-execution of completed threshold voltage change, thereby reducing overall erase time in the memory device.
Regarding claim 2, Ochi and Kim combined discloses the limitations of claim 1.
As applied, Ochi further discloses wherein
a timing at which the first command is received is during the erase voltage applying operation (Fig. 25. See also para 302; "As illustrated in FIG. 25, upon receiving the “FFh” command, the chip 100 immediately suspends the “Erase 1” operation").
Regarding independent claim 9, Ochi discloses a semiconductor memory device comprising:
a memory cell including a transistor (Fig. 4);
an interconnect (Fig. 5:58 CPWELL);
and a first circuit configured to perform an erase operation including (Fig. 2: 120 sequencer circuit)
an erase voltage applying operation of applying an erase voltage between a gate of the transistor and a channel of the transistor via the interconnect (para. 107; "The sequencer 120 raises the potential of the well interconnect CPWELL from voltage “VSS” to voltage “Vera1")
and an erase verify operation of determining a threshold voltage of the memory cell (Fig. 6. See also para. 125; "Specifically, at time instant “Ta11”, the sequencer 120 executes a first erase verify (Erase verify 1) operation"),
wherein the first circuit performs a first suspension processing of suspending the erase operation upon receiving a first command during the erase operation (para. 277; "Upon receiving the “FFh” command, the chip 100 immediately stops the operation which is currently executed (“Auto Suspend erase 1” operation)"),
in a case where a second suspension processing of suspending the erase operation has been performed before the first suspension processing (This limitation appears to be directed to step 108 of Figure 12 of the instant application. Accordingly, it will be interpreted to mean that there was a (first) suspension event, which resumed but did not complete, prior to the second suspension event),
the first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 22 where it illustrates the sequencer applying Vera3 again as part of the erase voltage applying operation after resuming suspended erase operation.),
and in a case where the second suspension processing has not been performed before the first suspension processing, the first circuit performs the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (See Examiner's Markup above where it illustrates the second suspension processing time period and the sequencer applying Vera6 as an erase voltage after resuming).
Ochi discloses resuming a suspended erase operation but is silent with respect to a timer circuit and the resuming of the erase operation where it was interrupted.
However, Kim teaches the first circuit including a timer circuit (Fig. 1A, Timer 144),
the timer circuit configured to measure a time during an erase execution period in which the erase voltage is applied in the erase voltage applying operation (para. 87; "The time duration being tracked by the timer can cumulatively grow across resuming the true erase sub-operation, and thus a total voltage ramping time"),
wherein the erase execution period includes a plurality of periods (Abstr. "The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse."),
and in a case where the first circuit performs the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing and where the erase operation is suspended in a first period of the plurality of periods, after the erase operation is resumed, in the erase voltage applying operation, the erase execution period is started from the first period (Fig. 6. step 640 Resume Erase. See also para 86; "At operation 640, the true erase sub-operation is resumed". It is noted that when a suspend command is executed during the erase, the timer is stopped (step 625). Upon resume (step 640) the timer is restarted. See also para. 87 "At operation 605, the timer is restarted. More specifically, the processing logic restarts the timer to be able to continue tracking the ramping period of the erase pulse at the memory line. The time duration being tracked by the timer can cumulatively grow across resuming the true erase sub-operation, and thus a total voltage ramping time." Thus, the resumption starts at the same place the erase operation left off which is analogous to the instant application.).
Ochi and Kim are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the erase suspension/resumption logic controlled by Ochi’s sequencer circuit with the timer-based tracking of discrete ramping periods and resumption from the interrupted point taught by Kim. Doing so would enable more efficient resumption of the erase voltage applying operation after suspension without unnecessary re-execution of completed threshold voltage change, thereby reducing overall erase time in the memory device.
Regarding claim 10 [directed toward Fig. 12], Ochi and Kim combined disclose the limitations of claim 9.
As applied Ochi further discloses
[Fig. 12: S108-Yes] in a case where the second suspension processing has been performed before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 12: S109-Yes] and the erase verify operation has been performed at the time of resuming the erase operation suspended by the second suspension processing (Fig. 10 where it illustrates the erase verify1 operation happening upon resuming the suspended erase operation),
[Fig. 12: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed")
[Fig. 12: S108-Yes] in a case where the second suspension processing has been performed before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 12: S109-No] and the erase verify operation has not been performed at the time of resuming the erase operation suspended by the second suspension processing (Fig. 9 where it illustrates the there is no erase verify operation upon resuming the erase operation after the suspension for Read2 for example),
[Fig. 12: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
Regarding claim 13 [directed toward Fig. 16], Ochi and Kim disclose the limitations of claim 9.
As applied, Ochi further discloses
[Fig. 16: S111-Yes] in a case where the second suspension processing of suspending the erase operation has been performed n times (n is an integer of 2 or more) before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9. See also Fig. 10 where it illustrates the number of nested suspension events to at least 5. Further, para. 204; “an “Auto Suspend erase A” (A is an integer of 7 or more) operation is continued”),
[Fig. 16: S112] the first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 9 where it illustrates an erase voltage applying operation after resuming erase after the Read2 operation),
[Fig. 16: S111-No] and in a case where the second suspension processing has not been performed n times before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read1 operation after time period Tb4. It is noted as mentioned above that a second suspension without a previous suspension is understood to mean that there is no previous suspension that did not fully complete the erase operation),
[Fig. 16: S104] the first circuit performs the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
Regarding claim 14, Ochi and Kim disclose the limitations of claim 1.
As applied, Ochi further discloses wherein the first command is not invalidated (Fig. 25. See also para. 302; “upon receiving the “FFh” command, the chip 100 immediately suspends the “Erase 1” operation”).
Regarding claim 15, Ochi and Kim disclose the limitations of claim 1.
As applied, Ochi further discloses wherein in a case where the erase operation is suspended in a first period during an erase execution period in which the erase voltage is applied in the erase voltage applying operation, after the erase operation is resumed, in the erase voltage applying operation, the first circuit is configured to start the erase execution period from the first period (Fig. 22 where it illustrates CPWELL at Vera3 prior to the suspension period, and then resuming with the erase applying operation at the same Vera3 level. It is noted that the instant application defines the first period as a verify skip phase and there are no verify operations indicated in Fig. 22)
Regarding Claim 16, Ochi and Kim disclose the limitations of claim 1.
As applied, Ochi further discloses wherein the transistor is a memory cell transistor (Fig. 4: MT0-MT47 for example).
Regarding Claim 17, Ochi discloses the limitations of claim 1.
As applied, Ochi further discloses wherein the semiconductor memory device is a NAND flash memory (Fig. 1; See also para. 42; “The memory system 2 includes”, “a plurality of NAND packages 10”)
Regarding claim 18, Ochi and Kim disclose the limitations of claim 1.
As applied, Kim further discloses wherein, in the case where the erase operation is suspended in the first period during the erase execution period, the timer circuit is configured to: end measurement during the first period of the time during an erase execution period the erase voltage is applied, and restart the measurement of the erase execution period (Fig. 6 where it illustrates step 625 which stops (ends) the timer, and step 605 which restarts the timer after resuming).
Regarding claim 19, Ochi and Kim disclose the limitations of claim 1.
As applied, Kim further discloses wherein the first circuit includes a latch circuit, the latch circuit is configured to: store information related to the measured time, and store information related to a time from a start of the erase execution period (para. 83; " At operation 625, the timer is stopped. More specifically, the processing logic, in response to receiving the suspend command, also stops the timer and optionally records the time duration tracked by the timer. It is noted that the act of recording the time is necessarily analogous to a common storage circuit such as a latch.),
and the timer circuit restarts measurement of the erase execution period based on the information related to the time from the start of the execution period to the first period (Fig. 6, step 605. See also para. 87; " At operation 605, the timer is restarted").
Claims 3-8, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi et al. (US 2017026229; “Ochi” – of record) in view of Kim et al. (US 20230063656; "Kim"), and further in view of Kondo (US 20190080773).
Regarding claim 3 [directed toward Fig. 9], Ochi and Kim disclose the limitations of claim 1.
As applied, Ochi further discloses [Fig. 9: S104] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 9: S105] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
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While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 9: S103-Yes] in a case where the voltage value of the interconnect is higher than a first threshold value (Fig. 9 where it illustrates the first threshold N1 exceeded after time T13. It is noted that while Kondo's threshold is a timer value, the Vera voltage is a function of time and therefore analogous. Additionally, no mechanism for how the interconnect voltage is determined is specifically disclosed in the instant application, but merely that the sequencer 36 determines whether Vera1/2 is higher than the threshold voltage. As the sequencer contains a timer 40 circuit, which is used to ramp up Vera, it is interpreted that Kondo applies the same method used to determine Vera1/2 and compare to the threshold value of interest.)
[Fig. 9: S103-No] and in a case where the voltage value of the interconnect is equal to or lower than the first threshold value (Fig. 9 where it illustrates the first threshold N1 not being exceeded at a time before T13).
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
Regarding claim 4 [directed toward Fig. 12], Ochi and Kim disclose the limitations of claim 1.
As applied Ochi further discloses [Fig. 12: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 12: S108-Yes] and a second suspension processing of suspending the erase operation has been performed when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 12: S109] the first circuit is further configured to perform the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 9 where it illustrates an erase voltage applying operation after resuming erase after the Read2 operation),
[Fig. 12: S108-No] and the second suspension processing has not been performed when it is before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read1 operation after time period Tb4. It is noted as mentioned above that a second suspension without a previous suspension is understood to mean that there is no previous suspension that did not fully complete the erase operation)
[Fig. 12: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed")
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 12: S107-Yes] in a case where the voltage value of the interconnect is higher than a second threshold value (Fig. 9 where it illustrates the second threshold N2 exceeded after time T16. It is noted that while Kondo's threshold is a timer value, the Vera voltage is a function of time and therefore analogous. Additionally, no mechanism for how the interconnect voltage is determined is specifically disclosed in the instant application, but merely that the sequencer 36 determines whether Vera1/2 is higher than the threshold voltage. As the sequencer contains a timer 40 circuit, which is used to ramp up Vera, it is interpreted that the same method is used to determine Vera1/2 and compared to the threshold value of interest.)
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
[Fig. 12: S107-No] and in a case where the voltage value of the second interconnect is equal to or lower than the first threshold value (Fig. 9 where it illustrates the second threshold N2 not being exceeded at a time before T16).
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
Regarding claim 5 [directed toward Fig. 12], Ochi, Kim and Kondo combined disclose the limitations of claim 4.
As applied, Ochi further discloses [Fig. 12: S108-Yes] the second suspension processing has been performed when it is before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read2 operation after time period Tb9),
[Fig. 12: S109-Yes] and the erase verify operation has been performed at the time of resuming the erase operation suspended by the second suspension processing (Fig. 10 where it illustrates the erase verify1 operation happening upon resuming the suspended erase operation),
[Fig. 12: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed")
[Fig. 12: S109-No] and the erase verify operation has not been performed at the time of resuming the erase operation suspended by the second suspension processing (Fig. 9 where it illustrates the there is no erase verify operation upon resuming the erase operation after the suspension for Read2 for example),
[Fig. 12: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 12: S107-No] and in a case where the voltage value of the second interconnect is equal to or lower than the first threshold value (Fig. 9 where it illustrates the second threshold N2 not being exceeded at a time before T16. It is noted that while Kondo's threshold is a timer value, the Vera voltage is a function of time and therefore analogous. Additionally, no mechanism for how the interconnect voltage is determined is specifically disclosed in the instant application, but merely that the sequencer 36 determines whether Vera1/2 is higher than the threshold voltage. As the sequencer contains a timer 40 circuit, which is used to ramp up Vera, it is interpreted that the same method is used to determine Vera1/2 and compared to the threshold value of interest).
Regarding claim 6 [directed toward Fig. 16], Ochi and Kim disclose the limitations of claim 1.
As applied Ochi further discloses [Fig. 16: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 16: S111-Yes] and a second suspension processing of suspending the erase operation has been performed when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 16: S112] the first circuit is further configured to perform the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 9 where it illustrates an erase voltage applying operation after resuming erase after the Read2 operation),
[Fig. 16: S111-No] and the second suspension processing has not been performed when it is before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read1 operation after time period Tb4. It is noted as mentioned above that a second suspension without a previous suspension is understood to mean that there is no previous suspension that did not fully complete the erase operation)
[Fig. 16: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 16: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 16: S110-No] in a case where the voltage value of the interconnect is equal to or lower than the first threshold value (Fig. 9 where it illustrates the first threshold N1 not being exceeded at a time before T13),
[Fig. 16: S111] in a case where the voltage value of the interconnect is higher than the first threshold value and equal to or lower than a second threshold value (fig. 9 where it illustrates a threshold N1 and a threshold N3 and the threshold N2 between N1 and N3. See also para. 94; “the value smaller than the threshold N1 is set to the threshold N2, but the present invention is not limited to this embodiment, and a value larger than the threshold N1 may be set to the threshold N2”, and para. 133; “the threshold N2 is further updated to a threshold N3”. Thus, the relational value of any of the thresholds can be set to any desired amount),
[Fig. 16: S107-Yes] and in a case where the voltage value of the interconnect is higher than the second threshold value (Fig. 9 where it illustrates the second threshold N2 exceeded after time T16).
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
Regarding claims 7 [directed toward Fig. 16], Ochi, Kim and Kondo combined disclose the limitations of claim 6.
As applied Ochi further discloses [Fig. 16: S111-Yes] the second suspension processing of suspending the erase operation has been performed when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 16: S112-Yes] and the erase verify operation has been performed from the second suspension processing to the first suspension processing (Fig. 10 where it illustrates the erase verify1 operation happening upon resuming the suspended erase operation),
[Fig. 16: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 16: S112-No] and the erase verify operation has not been performed from the second suspension processing to the first suspension processing (Fig. 9 where it illustrates the there is no erase verify operation upon resuming the erase operation after the suspension for Read2 for example),
[Fig. 16: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 16: S111] in a case where the voltage value of the interconnect is higher than the first threshold value and equal to or lower than a second threshold value (fig. 9 where it illustrates a threshold N1 and a threshold N3 and the threshold N2 between N1 and N3. See also para. 94; “the value smaller than the threshold N1 is set to the threshold N2, but the present invention is not limited to this embodiment, and a value larger than the threshold N1 may be set to the threshold N2”, and para. 133; “the threshold N2 is further updated to a threshold N3”. Thus, the relational value of any of the thresholds can be set to any desired amount)
Regarding claims 8 [directed toward Fig. 16], Ochi, Kim and Kondo combined disclose the limitations of claim 6.
As applied Ochi further discloses [Fig. 16: S111-Yes] the second suspension processing of suspending the erase operation has been performed when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 16: S112-Yes] and the erase verify operation has been performed at the time of resuming the erase operation suspended by the second suspension processing, (Fig. 10 where it illustrates the erase verify1 operation happening upon resuming the suspended erase operation),
[Fig. 16: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 16: S112-No] and the erase verify operation has not been performed from the second suspension processing to the first suspension processing (Fig. 9 where it illustrates the there is no erase verify operation upon resuming the erase operation after the suspension for Read2 for example),
[Fig. 16: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 16: S111] in a case where the voltage value of the interconnect is higher than the first threshold value and equal to or lower than a second threshold value (fig. 9 where it illustrates a threshold N1 and a threshold N3 and the threshold N2 between N1 and N3. See also para. 94; “the value smaller than the threshold N1 is set to the threshold N2, but the present invention is not limited to this embodiment, and a value larger than the threshold N1 may be set to the threshold N2”, and para. 133; “the threshold N2 is further updated to a threshold N3”. Thus, the relational value of any of the thresholds can be set to any desired amount),
Regarding claim 11 [directed toward Fig. 16], Ochi and Kim disclose the limitations of claim 1.
As applied Ochi further discloses [Fig. 16: S105] the first circuit performs the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 16: S111-Yes] a second suspension processing of suspending the erase operation has been performed n times (n is an integer of 2 or more) when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9. See also Fig. 10 where it illustrates the number of nested suspension events to at least 5. Further, para. 204; “an “Auto Suspend erase A” (A is an integer of 7 or more) operation is continued”)
[Fig. 16: S112] the first circuit is further configured to perform the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 9 where it illustrates an erase voltage applying operation after resuming erase after the Read2 operation),
[Fig. 16: S111-No] the second suspension processing has not been performed n times when it is before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read1 operation after time period Tb4. It is noted as mentioned above that a second suspension without a previous suspension is understood to mean that there is no previous suspension that did not fully complete the erase operation)
[Fig. 16: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 16: S107-Yes] and in a case where the voltage value of the interconnect is higher than the second threshold value (Fig. 9 where it illustrates the second threshold N2 exceeded after time T16),
[Fig. 16: S107-No] in a case where the voltage value of the interconnect is equal to or lower than the second threshold value,
[Fig. 16: S111-Yes] and the voltage value of the interconnect is lower than a second threshold value (fig. 9 where it illustrates a threshold N1 and a threshold N3 and the threshold N2 between N1 and N3. See also para. 94; “the value smaller than the threshold N1 is set to the threshold N2, but the present invention is not limited to this embodiment, and a value larger than the threshold N1 may be set to the threshold N2”, and para. 133; “the threshold N2 is further updated to a threshold N3”. Thus, the relational value of any of the thresholds can be set to any desired amount).
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
Regarding claim 12 [directed toward Fig. 19], Ochi and Kim disclose the limitations of claim 1.
As applied Ochi further discloses [Fig. 19: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed"),
[Fig. 19: S108-Yes] and a second suspension processing of suspending the erase operation has been performed n times (n is an integer of 2 or more) when it is before the first suspension processing (Fig. 9 where it illustrates the second suspension happening with the Read2 operation after time period Tb9)
[Fig. 19: S109] the first circuit is further configured to perform the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 9 where it illustrates an erase voltage applying operation after resuming erase after the Read2 operation),
[Fig. 19: S108-No] and the second suspension processing has not been performed n times when it is before the first suspension processing (Fig. 9 where it illustrates the suspension happening with the Read1 operation after time period Tb4. It is noted as mentioned above that a second suspension without a previous suspension is understood to mean that there is no previous suspension that did not fully complete the erase operation)
[Fig. 19: S104] the first circuit is further configured to perform the erase voltage applying operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 10 (SPS9) being a resume point which leads to the Erase1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
[Fig. 19: S105] the first circuit is further configured to perform the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing (Fig. 28 where it illustrates suspend candidate point 9 (SPS9) being a resume point which leads to the Erase verify 1 operation. See also para. 341; "a suspend candidate point at which the “Erase” operation is started, or a suspend candidate point at which the “Erase” operation is resumed").
While Ochi’s sequencer determines the value of Vera (and hence Vera1 and Vera2 of the instant application), and it is well understood in the art that a logic control unit such as Ochi’s would be capable of storing a threshold value and executing a compare against it, Ochi nor Kim specifically disclose Vera related thresholds.
However, Kondo teaches [Fig. 19: S110-No] in a case where the voltage value of the interconnect is equal to or lower than a first threshold value (Fig. 9 where it illustrates the first threshold N1 not being exceeded at a time before T13),
[Fig. 19: S110-Yes, and S107-No] in a case where the voltage value of the interconnect is higher than the first threshold value and equal to or lower than a second threshold value (Fig. 9 where it illustrates the first threshold N1 being exceeded at a time after T13, and Fig. 9 where it illustrates the second threshold N2 not being exceeded at a time before T16),
[Fig. 19: S107-Yes] and in a case where the voltage value of the interconnect is higher than the second threshold value (Fig. 9 where it illustrates the second threshold N2 being exceeded at a time after T16).
Ochi, Kim and Kondo are from the same field of endeavor as Applicant’s invention directed to resuming a suspended erase operation in a NAND memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ochi’s sequencer circuit and Kim's timer circuit with Kondo’s Vera thresholds. Doing so would reduce the total time required for completion of an erase operation while also expediting other priority memory operations.
Response to Arguments
Applicant's arguments filed March 13, 2026, have been fully considered but they are not persuasive. Although the amendments to independent claims 1, and 9 narrow the claim scope and are not disclosed by the previously applied references, the newly added features required further consideration and search. This search resulted in the application of new references. The claimed subject matter remains unpatentable under 35 U.S.C. § 103 over the combination of the previously applied references and the newly cited references. This constitutes a new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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