Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1- are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Pat. Pub. No. 20240258204 to Kim et al. (Kim) .
Regarding Claim 1, Kim teaches in Figs. 1A-2C at least, semiconductor device, comprising:
a substrate 194 having first and second surfaces opposite to each other (facing up and down on page);
a plurality of fin-type active patterns 105 extending in a first direction (in and out of page) on the first surface of the substrate;
a gate structure 160 extending in a second direction (left to right on page), intersecting the first direction, and crossing the plurality of fin-type active patterns;
a plurality of separation structures 110 arranged in parallel with the gate structure, and extending in the second direction, respectively;
source/drain regions 150 disposed on the plurality of fin-type active patterns on both sides of the gate structure;
an interlayer insulating layer 192 disposed on the substrate, and covering the source/drain regions;
a contact structure 197 penetrating the interlayer insulating layer, and connected to at least one of the source/drain regions;
a buried conductive structure 170 electrically connected to the contact structure, and extending in a vertical direction within the interlayer insulating layer between adjacent separation structures among the plurality of separation structures, the buried conductive structure having a first width in the first direction defined by a distance between the adjacent separation structures (lower portion may be defined as “first width” between and defined by 110); and
a power transmission structure 180 connected to the buried conductive structure, and extending from the second surface toward the first surface of the substrate.
Regarding Claim 3, Kim teaches the semiconductor device of claim 1, wherein the buried conductive structure comprises a first portion having the first width, and a second portion disposed on the first portion and having a second width, greater than the first width (170 is tapered with an upper portion having a greater width).
Regarding Claim 4, Kim teaches the semiconductor device of claim 3, wherein the second portion of the buried conductive structure has an extension portion extending in a direction parallel to the first surface of the substrate and connected to the contact structure (see Fig. 2C).
Regarding Claim 5, Kim teaches the semiconductor device of claim 1, wherein the buried conductive structure extends to the first surface of the substrate, and the power transmission structure is contact with the buried conductive structure on the first surface of the substrate (see Fig. 2C).
Regarding Claim 7, Kim teaches the semiconductor device of claim 6, wherein the buried conductive structure comprises a first conductive material 170 and a first conductive barrier 172 surrounding a side surface of the first conductive material.
Regarding Claim 9, Kim teaches the semiconductor device of claim 1, further comprising:
a first interconnection structure 198 disposed on the interlayer insulating layer, and including a first interconnection layer connected to the contact structure, wherein the buried conductive structure is electrically connected to the contact structure through the first interconnection layer.
Regarding Claim 11, Kim teaches the semiconductor device of claim 1, wherein the power transmission structure comprises a rail structure extending in the first direction between adjacent fin-type active patterns among the plurality of fin-type active patterns (see Fig. 1).
Regarding Claim 12, Kim teaches the semiconductor device of claim 1, wherein the power transmission structure comprises a rail structure extending in the second direction between the adjacent separation structures among the plurality of separation structures (see Fig. 1).
Regarding Claim 13, Kim teaches the semiconductor device of claim 1, further comprising a plurality of channel layers disposed on the plurality of fin-type active patterns and spaced apart from each other in a direction, perpendicular to an upper surface of the substrate, wherein the gate structure includes a gate electrode surrounding each of the plurality of channel layers and extending in the second direction, and a gate insulating film disposed between the plurality of channel layers and the gate electrode (see Fig. 2A).
Regarding Claim 14, Kim teaches a semiconductor device, comprising:
a substrate having first and second surfaces opposite to each other;
a plurality of fin-type active patterns extending in a first direction on the first surface of the substrate;
a plurality of gate structures extending in a second direction, intersecting the first direction, and crossing the plurality of fin-type active patterns;
a plurality of separation structures arranged in parallel with the plurality of gate structures, and extending in the second direction, respectively;
source/drain regions disposed on the plurality of fin-type active patterns on both sides of each of the plurality of gate structures;
an interlayer insulating layer disposed on the first surface of the substrate, covering the source/drain regions, and surrounding the plurality of gate structures and the plurality of separation structures;
a contact structure penetrating the interlayer insulating layer, and connected to at least one of the source/drain regions;
a buried conductive structure electrically connected to the contact structure, and extending in a vertical direction within the interlayer insulating layer; and
a power transmission structure extending from the second surface of the substrate toward the first surface of the substrate between two adjacent separation structures among the plurality of separation structures, and connected to the buried conductive structure,
wherein the buried conductive structure includes a first portion having a first width in the first direction defined by a distance between the two adjacent separation structures and a second portion disposed on the first portion and having a second width in the first direction, greater than the first width (see above rejections of claims 1 and 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6- are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Pat. No. 11177286 to Kim et al. (Kim2).
Regarding Claim 6, Kim teaches the semiconductor device of claim 1, but does not explicitly teach that the buried conductive structure extends into the substrate, and the power transmission structure is contact with the buried conductive structure in the substrate. However, in analogous art, Kim 2 teaches that a buried conductive structure 150 extends into a substrate 105 to contact a power transmission structure 160. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Kim2 to provide greater protection to the contact area between the buried conductive structure and the power rail.
Regarding Claim 10, Kim teaches the semiconductor device of claim 1, but does not explicitly teach:
a second interconnection structure disposed on the second surface of the substrate, and including a second interconnection layer connected to the power transmission structure.
However, Kim2 teaches a second interconnection structure 182/184 connected to the power rail 160. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Kim2 for greater flexibility of design.
Regarding Claims 18 and 19, Kim and Kim2 teach the semiconductor device of claim 17, further comprising: a first interconnection structure disposed on the intermediate insulating layer, and including a first interconnection layer electrically connected to the contact structure, and a second interconnection structure disposed on the second surface of the substrate, and including a second interconnection layer connected to the power transmission structure wherein the buried conductive structure is electrically connected to the contact structure through the first interconnection layer (see Fig. 19 of Kim2).
Allowable Subject Matter
Claims 2, 8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, Kim teaches the semiconductor device of claim 1, but does not teach that a width of the buried conductive structure in the second direction is defined by a distance between source/drain regions disposed in adjacent fin-type active patterns among the plurality of fin-type active patterns.
Regarding Claim 8, Kim teaches the semiconductor device of claim 7, but does not teach that the power transmission structure comprises a second conductive material and a second insulating liner surrounding a side surface of the second conductive material, and an upper surface of the power transmission structure has a first region in contact with a bottom surface of the buried conductive structure and a second region around the first region, and the second insulating liner has a portion extending onto the second region of the upper surface of the power transmission structure.
Regarding Claim 15, Kim teaches the semiconductor device of claim 14, but does not teach that at least one separation structure is located between the two adjacent separation structures, and the buried conductive structure extends in a vertical direction through a region from which the at least one separation structure is partially removed.
Regarding Claim 16, Kim teaches the semiconductor device of claim 14, but does not teach that a width of the buried conductive structure in the second direction is defined by a distance between source/drain regions disposed in adjacent fin-type active patterns among the plurality of fin-type active patterns.
Regarding Claim 17, Kim teaches the semiconductor device of claim 14, but does not teach an intermediate insulating layer disposed on the interlayer insulating layer and the plurality of separation structures, wherein the first portion of the buried conductive structure is located within the intermediate insulating layer.
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 20, Kim teaches a semiconductor device, comprising:
a substrate having first and second surfaces opposite to each other;
a plurality of fin-type active patterns extending in a first direction on the first surface of the substrate; a gate structure extending in a second direction, intersecting the first direction, and crossing the plurality of fin-type active patterns;
a plurality of separation structures arranged in parallel with the gate structure, and extending in the second direction, respectively;
source/drain regions disposed on the plurality of fin-type active patterns on both sides of the gate structure; an interlayer insulating layer disposed on the first surface of the substrate, and covering the source/drain regions;
a contact structure penetrating the interlayer insulating layer, and connected to at least one of the source/drain regions;
a buried conductive structure electrically connected to the contact structure, penetrating the interlayer insulating layer and a device isolation layer between two adjacent separation structures among the plurality of separation structures and extending toward a second surface of the substrate, wherein the buried conductive structure includes a portion having a first width in the first direction defined by a distance between the two adjacent separation structures (see above rejections of claims 1 and 14); but does not teach
an insulating protective film disposed on the second surface of the substrate, and surrounding a contact region of the buried conductive structure; a backside insulating layer disposed on the insulating protective film; and a power transmission rail disposed in the backside insulating layer, and connected to the contact region of the buried conductive structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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