CTNF 18/599,913 CTNF 88260 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Ariyoshi (US 2017/0287926) in view of Rabkin (US 2020/0143893) . Regarding claim 1, Ariyoshi discloses, in FIGS. 18A-18B and in related text, a semiconductor storage device comprising: a stacked body including a plurality of conductive layers (146, 246) stacked apart from each other, the plurality of conductive layers being processed into a step shape in a stepped portion (see Ariyoshi, [0082]-[0085], [0124]); a first pillar (55) that extends in a stacking direction of the stacked body in the stacked body different from the stepped portion and forms a memory cell (see Ariyoshi, [0127], [0137]); and a plurality of second pillars that extends in the stacking direction in the stepped portion, wherein the plurality of second pillars each includes: a first sub-pillar (131) that is a single substance of a first insulating layer (non-conductive intrinsic semiconductor material) extending in the stacking direction in a lower layer side (below etch stop layer 21) of the stacked body (see Ariyoshi, [0066], [0071]); and a second sub-pillar arranged at a height position in an upper layer side (above etch stop layer 21) of the stacked body to correspond to the first sub-pillar, and the second sub-pillar includes: a semiconductor layer (601, 602) extending in the stacking direction at the height position in the upper layer side of the stacked body; a second insulating layer (tunneling dielectric layer: ONO or oxide-nitride-oxide) covering a sidewall of the semiconductor layer; a third insulating layer (blocking dielectric layer: silicon oxide) covering a sidewall of the second insulating layer; and a fourth insulating layer (charge storing layer: silicon nitride) that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers ([0100]-[0105]). Ariyoshi discloses the plurality of conductive layers are word lines (see Ariyoshi, [0124]). Ariyoshi does not explicitly disclose a memory cell at each intersection portion with at least a part of the plurality of conductive layers Rabkin teaches memory cells formed at different levels at the intersection with a word line (see Rabkin, FIG. 6A, [0114]). Thus, Rabkin together with Ariyoshi teaches a memory cell at each intersection portion with at least a part of the plurality of conductive layers (word lines). Ariyoshi and Rabkin are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ariyoshi with the features of Yang because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Ariyoshi to include a memory cell at each intersection portion with at least a part of the plurality of conductive layers, as taught by Rabkin, to form a NAND string in a memory array (see Rabkin, [0114]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-07 AIA 07-97 12-51-07 Claim s 15-20 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of records, individually or in combination, do not disclose nor teach “a plurality of third pillars that extends in the stacking direction in the stepped portion at a position overlapping in the staking direction with a portion where upper-side conductive layers of the plurality of conductive layers are processed into a step shape, wherein the plurality of third pillars each includes: the semiconductor layer that extends in the stacking direction from the upper layer side to the lower layer side of the stacked body; the second insulating layer covering the sidewall of the semiconductor layer; the third insulating layer covering the sidewall of the second insulating layer; and the fourth insulating layer interposed between the second and third insulating layers” in combination with other limitations as recited in claim 2. The prior art of record, Ariyoshi, discloses wherein the stepped portion is covered with a sixth insulating layer that reaches a height position of an upper surface of the stacked body. The prior art of records, individually or in combination, do not disclose nor teach “the first insulating layer is further disposed in the sixth insulating layer at a height position corresponding to a bottom surface of the upper layer side of the stacked body to intersect with the plurality of second pillars” in combination with other limitations as recited in claim 14. The prior art of record, Ariyoshi, discloses a semiconductor storage device comprising: a first stacked body including a plurality of first conductive layers stacked apart from each other, the plurality of first conductive layers being processed into a step shape in a first stepped portion; a second stacked body including a plurality of second conductive layers stacked apart from each other, the second stacked body being arranged above the first stacked body and the plurality of second conductive layers being processed into a step shape in a second stepped portion to be continuous to the first stepped portion; a first pillar that extends in a stacking direction of the first and second stacked bodies in the first and second stacked bodies different from the first and second stepped portions and forms a memory cell; a plurality of second pillars that extends in the stacking direction at a first position overlapping in the stacking direction with the first stepped portion, wherein the plurality of second pillars each includes: a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in the first stacked body; and a second sub-pillar arranged at a height position of the second stacked body to correspond to the first sub-pillar, the second sub-pillar includes: a semiconductor layer that extends in the stacking direction at the height position of the second stacked body; a second insulating layer covering a sidewall of the semiconductor layer; a third insulating layer covering a sidewall of the second insulating layer; and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers. The prior art of record, Rabkin, teaches a memory cell at each intersection portion with at least a part of the plurality of first and second conductive layers. The prior art of records, individually or in combination, do not disclose nor teach “a plurality of third pillars that extends in the stacking direction at a second position overlapping in the stacking direction with the second stepped portion, the plurality of third pillars each includes: the semiconductor layer that extends in the stacking direction in the first and second stacked bodies; the second insulating layer covering the sidewall of the semiconductor layer; the third insulating layer covering the sidewall of the second insulating layer; and the fourth insulating layer interposed between the second and third insulating layers” in combination with other limitations as recited in claim 15 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811 Application/Control Number: 18/599,913 Page 2 Art Unit: 2811 Application/Control Number: 18/599,913 Page 3 Art Unit: 2811 Application/Control Number: 18/599,913 Page 4 Art Unit: 2811 Application/Control Number: 18/599,913 Page 5 Art Unit: 2811 Application/Control Number: 18/599,913 Page 6 Art Unit: 2811 Application/Control Number: 18/599,913 Page 7 Art Unit: 2811 Application/Control Number: 18/599,913 Page 8 Art Unit: 2811
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