DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-11, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim et al. (A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique) in view of Baldwin et al. (US 6608521 B1)
Regarding claim 1: Kim (fig. 3), discloses a programmable gain amplifier (SC-PGA) comprising: a first-stage operational transconductance amplifier (OTA) (A1); a second-stage operational transconductance amplifier (A2) having an input terminal connected to an output terminal of the first-stage operational transconductance amplifier (A1); a capacitor module (Cc) connected between the output terminal of the first-stage operational transconductance amplifier (A1) and an output terminal of the second-stage operational transconductance amplifier (A2).
However, Kim does not teach about a clock oscillation circuit connected to both the output terminal of the first stage operational transconductance amplifier and the capacitor module, or a correction circuit connected to both the clock oscillation circuit and the capacitor module.
Baldwin, Fig 5. teaches a clock oscillation circuit (oscillator 70/control circuit) connected to both the output terminal of the first-stage operational transconductance amplifier (Kim, Fig. 3, A1 output corresponding to Baldwin, node A) and the capacitor module (CT2) , and configured to perform charging and discharging of the capacitor module (CT2) by an output current (charge current IC2 and discharge current ID2) from the first-stage operational transconductance amplifier (Kim, Fig. 3, A1) (In the combination, Baldwin’s IC2 and ID2 provide the charging and discharging current at Kim’s (A1) output node to charge and discharge the capacitor module) to output a clock signal (VST); and a correction circuit (including switching circuit (65) and gain circuit (64)) connected to both the clock oscillation circuit (oscillation) and the capacitor module (CT2), and configured to adjust a capacitance (switching circuit (65) and gain circuit (64)); column 4, lines 41-45) of the capacitor module (CT2) to enable a clock frequency of the clock signal (VST) to be consistent with a preset clock frequency. Baldwin teaches an oscillator providing a periodic carrier signal having a predetermined constant period, corresponding to a predetermined operating frequency, and further teaches circuitry for correcting the oscillator output to maintain the desired waveform characteristics (column 1, lines 44-46, line 67 – column 2, line 1; column 4 line 3).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Baldwin’s frequency correction circuitry into Kim’s programmable gain amplifier to improve clock-frequency stability while retaining Kim’s programmable amplifier architecture.
Regarding claim 2: Kim doesn’t disclose the clock oscillation circuit comprises: a comparator connected to the capacitor module and configured to compare a voltage across the capacitor module with a preset threshold voltage to output a comparison signal; a charging/discharging switch connected in parallel with the capacitor module; and a logic control circuit connected to both the comparator and the charging/discharging switch, and configured to control the charging/discharging switch to be turned on or off based on the comparison signal, to perform charging and discharging of the capacitor module to output the clock signal.
Baldwin, Fig. 5, discloses wherein the clock oscillation circuit (oscillator 70) comprises: a comparator (58 and 60) connected to the capacitor module (CT2) and configured to compare a voltage (at node A) across the capacitor module (CT2) with a preset threshold voltage (VREF2 and 1/2VREF2) to output a comparison signal (from comparator 58 and/or comparator 60); a charging/discharging switch (transistors 52, 54) connected in parallel with the capacitor module (CT2) ; and a logic control circuit (reset flip-flop 62 together with switching circuit 65) connected to both the comparator (58, 60) and the charging/discharging switch (transistors 52, 54), and configured to control the charging/discharging switch (65) to be turned on or off based on the comparison signal (output of comparator 58 and/or 60), to perform charging and discharging of the capacitor module (CT2) to output the clock signal (VST).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to utilize Baldwin’s oscillator into Kim’s programmable gain amplifier in order to provide controlled charging and discharging of the capacitor while improving clock-frequency stability and waveform accuracy using Baldwin’s comparator-based correction circuitry.
Regarding claim 3: Kim does not disclose the preset threshold voltage is one of a first threshold voltage and a second threshold voltage; the comparator is configured to compare the voltage across the capacitor module with the one of the first threshold voltage and the second threshold voltage to output one of a first comparison signal and a second comparison signal as the comparison signal, the first comparison signal indicating that the voltage across the capacitor module has risen to be greater than or equal to the first threshold voltage, the second comparison signal indicating that the voltage across the capacitor module has dropped to be less than or equal to the second threshold voltage; the logic control circuit is configured to output, based on the first comparison signal, a first control signal to control the charging/discharging switch to be turned on to perform discharging of the capacitor module, or output, based on the second comparison signal, a second control signal to control the charging/discharging switch to be turned off to perform charging of the capacitor module; and the clock oscillation circuit further comprises a threshold selection circuit connected to both the logic control circuit and the comparator for selecting based on the first control signal the second threshold voltage as the preset threshold voltage or selecting based on the second control signal the first threshold voltage as the preset threshold voltage.
Baldwin, Fig. 5, discloses wherein the preset threshold voltage (VREF2 or ½ VREF2) is one of a first threshold voltage (VREF2) and a second threshold voltage (1/2 VREF2); the comparator (58 and/or 60) is configured to compare the voltage (node A) across the capacitor module (CT2) with the one of the first threshold voltage (VREF2) and the second threshold voltage (1/2 VREF2) to output (output of comparator 58 and/or comparator 60) one of a first comparison signal (output of comparator 58) and a second comparison signal (output of comparator 60) as the comparison signal (output of comparator 58 and/or 60), the first comparison signal (output of comparator 58) indicating that the voltage (node A) across the capacitor module (CT2) has risen to be greater than or equal to the first threshold voltage (VREF2), the second comparison signal (output of comparator 60) indicating that the voltage (node A) across the capacitor module (CT2) has dropped to be less than or equal to the second threshold voltage (1/2 VREF); the logic control circuit (reset flip-flop 62 together with switching circuit 65) is configured to output (control output from logic 62/65), based on the first comparison signal (output of comparator 58), a first control signal (charging control signal) to control the charging/discharging switch (transistors 52, 54/switching circuit 65) to be turned on to perform discharging of the capacitor module (CT2), or output (control output), based on the second comparison signal (output of comparator 60), a second control signal (discharging control signal) to control the charging/discharging switch (65) to be turned off to perform charging of the capacitor module (CT2); and the clock oscillation circuit (oscillator 70) further comprises a threshold selection circuit (cooperative operation of comparators 58 and 60, reset flip-flop 62, switching circuit 65, and gain circuit 64) connected to both the logic control circuit (reset flip-flop 62 together with switching circuit 65) and the comparators (58, 60) for selecting based on the first control signal (logic state output from reset flip-flop 62 controlling switching circuit 65) the second threshold voltage (1/2VREF2) as the preset threshold voltage (VREF2 or ½ VREF2) or selecting based on the second control signal (alternate logic state output from reset flip-flop 62 controlling switching circuit 65) the first threshold voltage (VREF2) as the preset threshold voltage (VREF2 or ½ VREF2).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to utilize Baldwin’s comparator-controlled oscillator within Kim’s programmable gain amplifier to provide selectable threshold-controlled charging and discharging of the capacitor module, thereby improving oscillation stability and waveform accuracy while maintaining Kim’s programmable gain amplifier architecture.
Regarding claim 5: Kim Fig. discloses wherein the capacitor module (CT2) comprises: a compensation capacitor (Cc) connected between the output terminal of the first-stage operational transconductance amplifier (A1) and the output terminal of the second-stage operational transconductance amplifier (A2).
However, Kim does not teach a capacitance matching device connected in parallel with the compensation capacitor; and wherein the correction circuit is connected to the capacitance matching device and configured to adjust a capacitance of the capacitance matching device to adjust the capacitance of the capacitor module.
Baldwin, Fig. 5, discloses a capacitance matching device (including switching circuit 65 and gain circuit 64 configured to adjust capacitor CT2) connected in parallel with the compensation capacitor (CT2), wherein the correction circuit (including switching circuit (65) and gain circuit (64)) is connected to the capacitance matching device (switching circuit 65 and gain circuit 64 adjusting CT2) and configured to adjust a capacitance of the capacitance matching device (switching circuit 65 and gain circuit 64 adjusting CT2) to adjust the capacitance of the capacitor module (CT2) .
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to provide adjustment of the compensation capacitor in response to process variation, thereby improving frequency accuracy while maintaining the programmable gain amplifier’s desired operating characteristics.
Regarding claim 6 -10: Kim does not disclose a mode switching circuit for switching the programmable gain amplifier (SC-PGA) between a correction mode and an operation mode.
Baldwin, Fig. 5, discloses operation of the programmable gain amplifier in a calibration/correction state in which switching circuit (65) and gain circuit (64) adjust capacitor (CT2) based on feedback to correct oscillator frequency, after which the circuit resumes normal signal operation. Thus, Baldwin teaches switching between correction functionality and normal operating functionality.
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Baldwin’s correction functionality into Kim’s programmable gain amplifier in order to perform frequency correction during a correction operation while permitting normal signal amplification during an operation mode, thereby improving frequency accuracy despite process variation while maintaining desired amplifier operation.
Regarding claim 11: Kim does not disclose the mode switching circuit comprises: a first switch connected between the capacitor module and the output terminal of the second-stage operational transconductance amplifier; and a second switch having one terminal grounded and another terminal connected between the capacitor module and the first switch, wherein the mode switching circuit is configured to switch the programmable gain amplifier to the operation mode by turning on the first switch and turning off the second switch, or switch the programmable gain amplifier to the correction mode by turning off the first switch and turning on the second switch.
Baldwin, Fig. 5, discloses the mode switching circuit (65) comprises: a first switch (transistor 52) (column 4, lines 31 – 34) connected between the capacitor module (CT2) and the output terminal of the second-stage operational transconductance amplifier (Kim, Fig. 3, A1 output corresponding to Baldwin, node A) ; and a second switch (Transistor 54-whose source is coupled to the discharge current source ID2 and thereby provides a grounded switching path) (column 4, lines 31 – 34) having one terminal grounded and another terminal connected between the capacitor module (CT2) and the first switch (transistor 52), wherein the mode switching circuit (65) is configured to switch the programmable gain amplifier (SC-PGA) to the operation mode by turning on the first switch and turning off the second switch (transistor 54), or switch the programmable gain amplifier (SC-PGA ) to the correction mode by turning off the first switch (transistor 52) and turning on the second switch. Thus, Baldwin teaches first and second switching elements arranged to selectively charge and discharge the capacitor module under control of reset flip-flop 62 (column 4, lines 31-39, 41-63; column 5, lines 1-6).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Baldwin’s mode switching architecture into Kim’s programmable gain amplifier so that the amplifier can be selectively operated in a correction mode and a normal operating mode, thereby providing controlled calibration while preserving normal amplifier operation.
Regarding claim 16: Kim, Fig. 3, discloses an integrated circuit, comprising a programmable gain amplifier, comprising: a first-stage operational transconductance amplifier (OTA) (A1) ; a second-stage operational transconductance amplifier (A2) having an input terminal connected to an output terminal of the first-stage operational transconductance amplifier (A1); a capacitor module (Cc) connected between the output terminal of the first-stage operational transconductance amplifier (A1) and an output terminal of the second-stage operational transconductance amplifier (A2).
However, Kim does not teach about a clock oscillation circuit connected to both the output terminal of the first stage operational transconductance amplifier and the capacitor module, or a correction circuit connected to both the clock oscillation circuit and the capacitor module.
Baldwin, Fig 5. teaches a clock oscillation circuit (oscillator 7/control circuit) connected to both the output terminal of the first-stage operational transconductance amplifier (Kim, Fig. 3, A1 output corresponding to Baldwin, node A) and the capacitor module (CT2) , and configured to perform charging and discharging of the capacitor module (CT2) by an output current (charge current IC2 and discharge current ID2) from the first-stage operational transconductance amplifier (Kim, Fig. 3, A1) (In the proposed combination, Baldwin’s IC2 and ID2 provide the charging and discharging current at Kim’s (A1) output node to charge and discharge the capacitor module) to output a clock signal (VST); and a correction circuit (including switching circuit (65) and gain circuit (64)) connected to both the clock oscillation circuit (oscillation) and the capacitor module (CT2), and configured to adjust a capacitance (switching circuit (65) and gain circuit (64); column 4, lines 41-45) of the capacitor module (CT2) to enable a clock frequency of the clock signal (VST) to be consistent with a preset clock frequency. Baldwin teaches an oscillator providing a periodic carrier signal having a predetermined constant period, corresponding to a predetermined operating frequency, and further teaches circuitry for correcting the oscillator output to maintain the desired waveform characteristics (column 1, lines 44-46, line 67 – column 2, line 1; column 4 line 3).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Baldwin’s frequency correction circuitry into Kim’s programmable gain amplifier implemented as part of an integrated circuit to improve clock-frequency stability while retaining Kim’s programmable gain amplifier architecture.
Regarding claim 17: Kim does not expressly disclose an electronic device comprising a device body; and the integrated circuit of claim 16, disposed within the device body.
Baldwin, Fig. 5, teaches a device body (switch mode power converter 50); and the integrated circuit of claim 16 (see the rejection of Claim 16 above), disposed within the device body (control circuit 50 implemented within the power converter).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to implement the combined programmable gain amplifier within Baldwin’s electronic device because Baldwin already teaches incorporating such control circuitry within a switch mode power converter, thereby providing the improved clock-frequency stability of the combined circuitry within an electronic device.
Regarding claim 18: Kim (fig. 3) discloses wherein the programmable gain amplifier comprises: a first-stage operational transconductance amplifier (A1); a second-stage operational transconductance amplifier (A2) having an input terminal connected to an output terminal of the first-stage operational transconductance amplifier (A1). However, Kim does not teach about a clock oscillation circuit connected to both the output terminal of the first stage operational transconductance amplifier and the capacitor module, or a correction circuit connected to both the clock oscillation circuit and the capacitor module.
Baldwin, Fig. 5, teaches performing the recited method using the programmable gain amplifier discussed above. Baldwin further discloses a compensation capacitor (CT2) by an output current from the first-stage operational transconductance amplifier connected between the output terminal of the first-stage operational transconductance amplifier (A1) and an output terminal of the second-stage operational transconductance amplifier (A2) , and the method comprises: performing charging and discharging of the compensation capacitor (CT2) by an output current from the first-stage operational transconductance amplifier (A1) to output a clock signal (VST); and adjusting a capacitance (switching circuit (65) and gain circuit (64)) of the compensation capacitor (CT2) to enable a clock frequency of the clock signal (VST) to be consistent with a preset clock frequency.
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to perform Baldwin’s disclosed charging/discharging and capacitance-adjustment method using Kim’s programmable gain amplifier to improve clock-frequency stability while retaining Kim’s programmable gain amplifier architecture.
Regarding claim 19: Kim does not explicitly teach configuring a capacitance matching device and the compensation capacitor as a capacitor array; comparing a voltage across the capacitor array with a threshold voltage to output a comparison signal; and controlling charging and discharging of the capacitor array based on the comparison signal to output the clock signal.
Baldwin, Fig. 5, discloses wherein the performing of charging and discharging of the compensation capacitor (CT2) to output the clock signal (VST) comprises: configuring a capacitance matching device (Baldwin switching circuit 65 and gain circuit 64 adjusting CT2) and the compensation capacitor (CT2) as a capacitor array (CT2 implemented as an adjustable capacitance/capacitance network in the proposed combination); comparing a voltage (node A- voltage across CT2 ) across the capacitor array with a threshold voltage (comparator 58 and 60) to output a comparison signal (from comparator 58 and/or comparator 60); and controlling charging and discharging of the capacitor array (CT2 implemented as an adjustable capacitance/capacitance network in the proposed combination) based on the comparison signal to output the clock signal (VST) .
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to perform Baldwin’s disclosed capacitance matching and comparator-controlled charging/discharging method using Kim’s programmable gain amplifier to improve clock-frequency stability while retaining Kim’s programmable gain amplifier architecture.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique) in view of Baldwin et al. (US 6608521 B1) as applied to claims 1-3, 5-11, 16-19, and further in view of Elwan et al. (US 2007/0296490 A1)
Regarding claim 12 - 15: Kim as modified by Baldwin does not disclose a buffer circuit connected to the output terminal of the second-stage operational transconductance amplifier.
Elwan, Fig. 4, discloses a buffer circuit connected to the output terminal of the second-stage operational transconductance amplifier (SC-PGA), wherein the outputs of VGA circuits 40 and 45 are buffered to permit the amplifier to drive resistive-input circuitry (paragraph 50, lines 6-8; paragraph 64, lines 28-30).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Elwan’s buffered output into the programmable gain amplifier of Kim as modified by Baldwin in order to improve output drive capability, permit the corrected programmable gain amplifier to drive downstream circuitry, isolate the amplifier output from loading effects, while retaining Baldwin’s frequency correction functionality and Kim’s programmable gain amplifier architecture.
Allowable Subject Matter
Claims 4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4: the prior art fails to disclose a counter connected to the logic control circuit and configured to count the clock signal based on a preset reference clock signal to output a counting result, wherein a frequency of the preset reference clock signal is greater than a frequency of the clock signal; a quantizer connected to the counter and configured to determine, based on the counting result, whether the clock frequency of the clock signal is consistent with the preset clock frequency and, in response to determining that the clock frequency of the clock signal is inconsistent with the preset clock frequency, output an adjustment signal; and an adjustment circuit connected to both the quantizer and the capacitor module and configured to adjust the capacitance of the capacitor module based on the adjustment signal to enable the clock frequency of the clock signal to be consistent with the preset clock frequency.
Regarding claim 20: The prior art fails to disclose the method of counting the clock signal using a preset reference clock to generate a counting result, determining clock-frequency consistency based on the counting result, outputting an adjustment signal, and adjusting capacitance based on that adjustment signal.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Luich et al. (US 2008/0068107 A1) was considered during the search because it discloses a programmable oscillator circuitry, including a programmable transconductance amplifier and programmable frequency adjustment. However, Luich does not teach frequency correction based on a counter generating a counting result for adjusting clock frequency as recited in claim 4 and claim 20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
NATASHA Y. MARANO
Examiner
Art Unit 2843
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