Prosecution Insights
Prosecution Insights
1 pending office actions • 0 art units • 1 examiners • 0 of 1 (0%) have an AI response strategy ready
Chipsea Technologies (Shenzhen) Corp. has 1 pending office action currently on file. This activity is managed by the distinct examiner and 0 distinct art units. NATASHA YOLANDA MARANO is the busiest examiner, with 1 busiest examiner pending action.
The 1 pending office action is the sole active matter for the company at this time. With the distinct examiner, NATASHA YOLANDA MARANO, overseeing the busiest examiner pending action, the prosecution is centralized under a single official. The 0 distinct art units figure indicates a specific administrative status for the pending application. This minimal footprint suggests a highly targeted approach to the current patent filing. Practitioners should note that the absence of multiple art units simplifies the tracking of procedural deadlines for this portfolio. The centralized prosecution allows for a consistent messaging strategy across all filings.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 1 (100%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| MARANO, NATASHA YOLANDA | 1 | 100.0% | +0.0% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18600593 | PROGRAMMABLE GAIN AMPLIFIER, INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND FREQUENCY CORRECTION METHOD | MARANO, NATASHA YOLANDA | — |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18600593 | PROGRAMMABLE GAIN AMPLIFIER, INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND FREQUENCY CORRECTION METHOD | MARANO, NATASHA YOLANDA | — | §103 | Non-Final OA | — | Pending | Mar 08, 2024 |
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