DETAILED ACTION
This non-final action is responsive to communications: 12/18/2025.
Claims 1-18 are pending. Claim 1 is independent.
Election/Restrictions
3. Applicant’s election without traverse of claims 1-18 (Species I) in the reply filed on 12/18/2025 is acknowledged. Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Claims 1-18 are pending in the application.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 03/10/2024. This IDS has been considered.
Specification Objections
6. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following is suggested:
“NAND FLASH MEMORY AND METHOD OF EXECUTING HIGH-SPEED MODE READ OPERATION”
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-3, 9-10, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAMATA et al. (US 2021/0233596 A1).
Regarding independent claim 1, KAMATA teaches a semiconductor memory device (Fig. 1 “semiconductor memory device” with Fig. 4 configuration. See Fig. 1-Fig. 12 for illustrated components and functionality) comprising:
a first memory string (Fig. 4: “Near” first string connected to first selected WL in BLK0. See in relation to Fig. 2, Fig. 8-Fig. 9) in which a plurality of memory cell transistors including a first memory cell transistor is coupled in series (See Fig. 2: NS for string structure with MT and word lines);
second memory string (Fig. 4: “Far” second string connected to first selected WL in BLK0. See in relation to Fig. 2, Fig. 8-Fig. 9) in which a plurality of memory cell transistors including a second memory cell transistor is coupled in series (See Fig. 2: NS for string structure with MT and word lines);
a first word line (Fig. 4: first selected WL in BLK0) commonly coupled to a gate of each of the first memory cell transistor (Fig. 4: first MT with “Near” first string) and the second memory cell transistor (Fig. 4: second MT with “Far” second string. See selected first WL in BLK0 would be commonly coupled to “Near” strings and “Far” strings); and
a control circuit (Fig. 4: 12A, 12B row decoder module. See also Fig. 1),
wherein during a first read operation of reading data from the first memory string (Fig. 12, para [0099]: “read operation” applicable for first string cells],
a threshold voltage of the first memory cell transistor is less than a first voltage (para [0108]: “…threshold voltage of the selected memory cell corresponding to the Near side is lower than the voltage CR…” and VBLon is applied to BL/ string during read. Para [0105] and at Fig. 12: t2: threshold voltage levels are evaluated),
a threshold voltage of the second memory cell transistor is equal to or greater than the first voltage (para [0109]: “…threshold voltage of the selected memory cell corresponding to the Far side is equal to or higher than the voltage CR…” and VBLoff is applied to BL/ string during read and BL is suppressed. Para [0105] and at Fig. 12: t2: threshold voltage levels are evaluated), and
the control circuit is configured to supply a voltage equal to or less than the first voltage to the first word line (para [0106]: “…row decoder module…applies… the read voltage CR to the word line WL…”. See at Fig. 12: t3).
Regarding claim 2, KAMATA teaches the semiconductor memory device of claim 1, further comprising:
a third memory cell transistor included in the first memory string (Fig. 4: third MT with “Near” first string);
a fourth memory cell transistor included in the second memory string (Fig. 4: fourth MT with “Far” second string); and
a second word line (Fig. 4: second selected WL in BLK0) commonly coupled to a gate of each of the third memory cell transistor (Fig. 4: third MT with “Near” first string) and the fourth memory cell transistor (Fig. 4: fourth MT with “Far” second string),
wherein during the first read operation, a threshold voltage of the third memory cell transistor is less than the first voltage, a threshold voltage of the fourth memory cell transistor is equal to or greater than the first voltage (Fig. 12, para [0108]-para [0109]), and
the control circuit is configured to supply the voltage equal to or less than the first voltage to the second word line (para [0106]: “…row decoder module…applies… the read voltage CR to the word line WL…”. See at Fig. 12: t3).
Regarding claim 3, KAMATA teaches the semiconductor memory device of claim 1, wherein a wiring length between the control circuit and the second memory cell transistor is longer than a wiring length between the control circuit and the first memory cell transistor (Fig. 4: length of wiring distance from decode 12A to strings/ string regions. See “Far” and “Near” location of strings. Para [0063]).
Regarding claim 9, KAMATA teaches the semiconductor memory device of claim 1, further comprising: a third memory string in which a plurality of memory cell transistors including a third memory cell transistor is coupled in series (Fig. 4: another “Far” string coupled to first selected WL),
wherein a gate of the third memory cell transistor is commonly coupled to the first word line together with the gate of each of the first memory cell transistor and the second memory cell transistor (Fig. 4: another “Far” string coupled to first selected WL), and
during the first read operation, a threshold voltage of the third memory cell transistor is equal to or greater than the first voltage (See para [0108], para [0109], Fig. 12).
Regarding claim 10, KAMATA teaches the semiconductor memory device of claim 1, wherein, during the first read operation, the control circuit is configured to cause all the memory cell transistors included in the second memory string to be in an OFF state (Fig. 12 in context of para [0109]: VBLoff).
Regarding claim 14, KAMATA teaches the semiconductor memory device of claim 1, wherein during a first write operation of writing data into the first memory string, the threshold voltage of the first memory cell transistor is less than the first voltage, the threshold voltage of the second memory cell transistor is equal to or greater than the first voltage, and the control circuit is configured to cause all the memory cell transistors included in the second memory string to be in an OFF state (para [0217]: “write verify” operation is encompassed by the limitation. See also para [0109]).
Allowable Subject Matter
Claims 4-8, 11-13, and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding these claims, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the following imitations:
Regarding claims 4-5, 8: “… a first select transistor included in the first memory string; a second select transistor included in the second memory string; and a first select gate line commonly coupled to a gate of each of the first select transistor and the second select transistor, wherein the first select transistor is coupled to one ends of the memory cell transistors of the first memory string, and the second select transistor is coupled to one ends of the memory cell transistors of the second memory string, and during the first read operation, a threshold voltage of the first select transistor is less than a second voltage, a threshold voltage of the second select transistor is equal to or greater than the second voltage, and the control circuit is configured to supply the second voltage to the first select gate line...”
Regarding claim 6: “…a fifth memory cell transistor included in the first memory string; a sixth memory cell transistor included in the second memory string; and a third word line commonly coupled to a gate of each of the fifth memory cell transistor and the sixth memory cell transistor, wherein the fifth memory cell transistor is provided between the first memory cell transistor and the third memory cell transistor, the sixth memory cell transistor is provided between the second memory cell transistor and the fourth memory cell transistor, and during the first read operation, a threshold voltage of the fifth memory cell transistor and a threshold voltage of the sixth memory cell transistor are less than the first voltage, and the control circuit is configured to supply the voltage equal to or less than the first voltage to the third word line…”
Regarding claim 7: “…in an acceleration operation before the first read operation, to raise the threshold voltage of the second memory cell transistor to be equal to or greater than the first voltage and to maintain the threshold voltage of the first memory cell transistor to be less than the first voltage…”
Regarding claims 11-13: “… during a second read operation of reading data from the first memory string, the second read operation being different from the first read operation, a threshold voltage of all the memory cell transistors included in the first memory string and the second memory string is less than the first voltage, and the control circuit is configured to supply the voltage equal to or less than the first voltage to the first word line…”
Regarding claims 15-18: “… during a second write operation of writing data into the first memory string, the second write operation being different from the first write operation, a threshold voltage of all the memory cell transistors included in the first memory string and the second memory string is less than the first voltage…”
Regarding claim 18: “… a plurality of third memory strings in each of which a plurality of memory cell transistors is coupled in series, wherein the first memory string, the second memory string, and the first word line are included in a first memory region, the third memory strings are included in a second memory region different from the first memory region, and during a second read operation of reading data from the third memory strings, the second read operation being different from the first read operation, a threshold voltage of all the memory cell transistors included in the third memory strings is less than the first voltage…”
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Wu (US 2022/0208276 A1: Fig. 1-Fig. 22 disclosure applicable for all claims.
Tokutomi (US 2022/0270687 A1): Fig. 1-Fig. 45 disclosure applicable for all claims.
Dutta (US 2011/0032757 A1): Fig. 1-Fig. 21b disclosure applicable for all claims. It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825