DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (Claims 1-10) in the reply filed on 05/13/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2005/0088889 A1) in view of Chen et al. (US 2025/0176232 A1).
Regarding Claim 1, Lee (2-7) discloses a method for forming a semiconductor device, comprising:
providing a substrate (100) comprising a first active region (52), a second active region (51) and a third active region (50);
forming a first gate dielectric material layer (104) in the first active region of the substrate (100);
removing portions of the first gate dielectric material layer (104) and portions of the substrate (100) next to the portions of the first gate dielectric material layer (104) to form a first gate dielectric layer of a first element (134a) and first trenches (108) at opposite sides of the first gate dielectric layer (104);
forming a second trench (108 in 51) defining the first active region (50), the second active region (51) and the third active region (50) in the substrate (100); and
filling the first trenches (108 in 52) and the second trench (108 in 20 and 51)) with an insulating material to form isolation structures in the first trenches and to form an element isolation structure in the second trench.
Lee does not explicitly disclose a first gate dielectric material layer embedded in the first active region of the substrate.
Chen (Fig. 5) discloses a first gate dielectric material layer (524) embedded in a first active region (502c) of a substrate (524). [0035]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor device in Lee in view of Chen such that a first gate dielectric material layer embedded in the first active region of the substrate in order to increase a reliability of the transistor [0021].
Regarding Claim 2, Lee in view Chen discloses the method of claim 1, further comprising:
forming a second gate dielectric layer (112) of a second element (136) and a third gate dielectric layer (116) of a third element respectively on the second active region (51) and the third active region of the substrate (50) after forming the isolation structures (110 in 52) and the element isolation structure (110 in 51).
Regarding Claim 3, Lee in view Chen discloses the method of claim 2, wherein
Lee in view Chen as previously combined does not explicitly disclose a horizontal area of the first element is greater than a horizontal area of the second element and a horizontal area of the third element.
However, Chen (Fig. 5A) discloses a horizontal area of a first element (502c) is greater than a horizontal area of a second element (502b) and a horizontal area of the third element. (502a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor device in Lee in view of Chen such that a horizontal area of the first element is greater than a horizontal area of the second element and a horizontal area of the third element in order to form a high voltage (HV) region [0030-0031]
Regarding Claim 4, Lee in view Chen discloses the method of claim 3, wherein
Lee in view Chen as previously combined does not explicitly disclose a top surface of the first gate dielectric layer is coplanar with top surfaces of the isolation structures.
However, Chen (Fig. 5A) discloses a top surface of the first gate dielectric layer (524) is coplanar with top surfaces of a isolation structures (104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor device in Lee in view of Chen such that a horizontal area of the first element is greater than a horizontal area of the second element and a horizontal area of the third element in order to in order to increase a reliability of the transistor [0021].
Regarding Claim 5, Lee in view Chen discloses the method of claim 2, further comprising:
Lee in view Chen discloses sequentially forming a high dielectric constant (high-k) layer (120), a capping layer (130a) and a gate electrode (132) on the third gate dielectric layer (116) to form a third gate structure in the third active region (50).
Lee in view Chen as previously combined does not explicitly disclose sequentially forming a high dielectric constant (high-k) layer, a capping layer and a gate electrode on each of the first gate dielectric layer, the second gate dielectric layer to form a first gate structure in the first active region structure, a second gate structure in the second active region.
However, Chen (Fig. 6) discloses sequentially forming a high dielectric constant (high-k) layer (120), a capping layer (130a) and a gate electrode (132a) on each of the first gate dielectric layer (524), the second gate dielectric layer (108) to form a first gate structure (HV transistor) in the first active region structure (502c), a second gate structure (MV transistor) in the second active region (502b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor device in Lee in view of Chen sequentially forming a high dielectric constant (high-k) layer, a capping layer and a gate electrode on each of the first gate dielectric layer, the second gate dielectric layer to form a first gate structure in the first active region structure, a second gate structure in the second active region in order to form HV gate structure in the HV region and MV gate structure in the MV region [0038-0039]
Regarding Claim 6, Lee in view Chen discloses the method of claim 5 further comprising:
forming a first source/drain (240C) in the first active region of the substrate (52) at opposite sides of the first gate structure (348);
forming a second source/drain (240b,c) in the second active region of the substrate (51) at opposite side of the second gate structure; and
forming a third source/drain (240a,b) in the third active region of the substrate (50) at opposite sides of the third gate structure.
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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